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參數(shù)資料
| 型號： | CYV15G0403DXB-BGXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, LEAD FREE, BGA-256 |
| 文件頁數(shù)： | 20/45頁 |
| 文件大小： | 517K |
| 代理商： | CYV15G0403DXB-BGXI |
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CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
Document #: 38-02065 Rev. *F
Page 20 of 45
BIST_START until the buffer is re-centered (approximately
nine character periods).
To ensure compatibility between the source and destination
systems when operating in BIST modes, the sending and
receiving ends of the link must use the same receive clock
configuration.
Device Configuration and Control Interface
The CYP(V)(W)15G0403DXB is highly configurable via the
configuration interface. The configuration interface allows the
device to be configured globally or allows each channel to be
configured independently.
Table 9
lists the configuration
latches within the device including the initialization value of the
latches upon the assertion of RESET.
Table 10 on page 24
shows how the latches are mapped in the device. Each row in
the
Table 10
maps to a 8-bit latch bank. There are 16 such
write-only latch banks. When WREN = 0, the logic value in the
DATA[7:0] is latched to the latch bank specified by the values
in ADDR[3:0]. The second column of
Table 10
specifies the
channels associated with the corresponding latch bank. For
example, the first three latch banks (0,1 and 2) consist of
configuration bits for channel A. The latch banks 12, 13 and 14
consist of Global configuration bits and the last latch bank (15)
is the Mask latch bank that can be configured to perform
bit-by-bit configuration.
Global Enable Function
The global enable function, controlled by the GLENx bits, is a
feature that can be used to reduce the number of write opera-
tions needed to setup the latch banks. This function is
beneficial in systems that use a common configuration in
multiple channels. The GLENx bit is present in bit 0 of latch
banks 0 through 11 only. Its default value (1) enables the global
update of the latch bank's contents. Setting the GLENx bit to
0 disables this functionality.
Latch Banks 12, 13, and 14 are used to load values in the
related latch banks in a global manner. A write operation to
latch bank 12 could do a global write to latch banks 0, 3, 6, and
9 depending on the value of GLENx in these latch banks; latch
bank 13 could do a global write to latch banks 1, 4, 7 and 10;
and latch banks 14 could do a global write to latch banks 2, 5,
8 and 11. The GLENx bit cannot be modified by a global write
operation.
Force Global Enable Function
FGLENx forces the global update of the target latch banks, but
does not change the contents of the GLENx bits. If FGLENx =
1 for the associated global channel, FGLENx forces the global
update of the target latch banks.
Mask Function
An additional latch bank (15) is used as a global mask vector
to control the update of the configuration latch banks on a
bit-by-bit basis. A logic 1 in a bit location allows for the update
of that same location of the target latch bank(s), whereas a
logic 0 disables it. The reset value of this latch bank is FFh,
thereby making its use optional by default. The mask latch
bank is not maskable. The FGLEN functionality is not affected
by the bit 0 value of the mask latch bank.
Latch Types
There are two types of latch banks: static (S) and dynamic (D).
Each channel is configured by 2 static and 1 dynamic latch
banks. The S type contain those settings that normally do not
change for a given application, whereas the D type controls
the settings that could change dynamically during the appli-
cation's lifetime.The first row of latches for each channel
(address numbers 0, 3, 7, and 10) are the static receiver
control latches. The second row of latches for each channel
(address numbers 1, 4, 8, and 11) are the static transmitter
control latches. The third row of latches for each channel
(address numbers 2, 5, 9, and 12) are the dynamic control
latches that are associated with enabling dynamic functions
within the device.
Latch Bank 14 is also useful for those users that do not need
the latch-based programmable feature of the device. This
latch bank could be used in those applications that do not need
to modify the default value of the static latch banks, and that
can afford a global (i.e., not independent) control of the
dynamic signals. In this case, this feature becomes available
when ADDR[3:0] is left unchanged with a value of “1110” and
WREN is left asserted. The signals present in DATA[7:0] effec-
tively become global control pins, and for the latch banks 2, 5,
8 and 11.
Table 9. Device Configuration and Control Latch Descriptions
Name
RFMODEA[1:0]
RFMODEB[1:0]
RFMODEC[1:0]
RFMODED[1:0]
Signal Description
Reframe Mode Select
. The initialization value of the RFMODEx [1:0] latches = 10. RFMODEx is used to
select the operating mode of the framer. When RFMODEx[1:0] = 00, the low-latency framer is selected. This
frames on each occurrence of the selected framing character(s) in the received data stream. This mode of
framing stretches the recovered clock for one or multiple cycles to align that clock with the recovered data.
When RFMODEx[1:0] = 01, the alternate mode Multi-Byte parallel framer is selected. This requires detection
of the selected framing character(s) in the received serial bit stream, on identical 10-bit boundaries, on four
directly adjacent characters. The recovered character clock remains in the same phasing regardless of
character offset. When RFMODEx[1:0] =10, the Cypress-mode Multi-Byte parallel framer is selected. This
requires a pair of the selected framing character(s), on identical 10-bit boundaries, within a span of 50 bits,
before the character boundaries are adjusted. The recovered character clock remains in the same phasing
regardless of character offset. RFMODEx[1:0] = 11 is reserved for test.
[+] Feedback
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