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參數(shù)資料
| 型號(hào)： | CYV15G0403DXB-BGXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, LEAD FREE, BGA-256 |
| 文件頁數(shù)： | 13/45頁 |
| 文件大?。?/td> | 517K |
| 代理商： | CYV15G0403DXB-BGXI |
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CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
Document #: 38-02065 Rev. *F
Page 13 of 45
CYP(V)(W)15G0403DXB HOTLink II Operation
The CYP(V)(W)15G0403DXB is a highly configurable,
independent clocking, quad-channel transceiver designed to
support reliable transfer of large quantities of data, using
high-speed serial links from multiple sources to multiple desti-
nations. This device supports four single-byte channels.
CYP(V)(W)15G0403DXB Transmit Data Path
Input Register
The bits in the Input Register for each channel support
different assignments, based on if the input data is encoded or
unencoded. These assignments are shown in
Table 1
.
When the ENCODER is enabled, each input register captures
eight data bits and two control bits on each input clock cycle.
When the Encoder is bypassed, the control bits are part of the
pre-encoded 10-bit character.
When the Encoder is enabled, the TXCTx[1:0] bits are inter-
preted along with the associated TXDx[7:0] character to
generate a specific 10-bit transmission character.
Phase-Align Buffer
Data from each Input Register is passed to the associated
Phase-Align Buffer, when the TXDx[7:0] and TXCTx[1:0] input
registers are clocked using TXCLKx| (TXCKSELx = 0 and
TXRATEx = 0). When the TXDx[7:0] and TXCTx[1:0] input
registers are clocked using REFCLKx± (TXCKSELx = 1) and
REFCLKx± is a full-rate clock, the associated Phase
Alignment Buffer in the transmit path is bypassed. These
buffers are used to absorb clock phase differences between
the TXCLKx input clock and the internal character clock for
that channel.
Once initialized, TXCLKx is allowed to drift in phase as much
as ±180 degrees. If the input phase of TXCLKx drifts beyond
the handling capacity of the Phase Align Buffer, TXERRx is
asserted to indicate the loss of data, and remains asserted
until the Phase Align Buffer is initialized. The phase of the
TXCLKx relative to its associated internal character rate clock
is initialized when the configuration latch PABRSTx is written
as 0. When the associated TXERRx is deasserted, the Phase
Align Buffer is initialized and input characters are correctly
captured.
If the phase offset, between the initialized location of the input
clock and REFCLKx|, exceeds the skew handling capabilities
of the Phase-Align Buffer, an error is reported on that
channel’s TXERRx output. This output indicates an error
continuously until the Phase-Align Buffer for that channel is
reset. While the error remains active, the transmitter for that
channel outputs a continuous C0.7 character to indicate to the
remote receiver that an error condition is present in the link.
Each Phase-Align Buffer may be individually reset with
minimal disruption of the serial data stream. When a
Phase-Align Buffer error is present, the transmission of a Word
Sync Sequence re-centers the Phase-Align Buffer and clears
the error indication.
Note
. K28.5 characters may be added or removed from the
data stream during the Phase Align Buffer reset operation.
When used with non-Cypress devices that require a complete
16-character Word Sync Sequence for proper receive
Elasticity Buffer Operation, it is recommend that the Phase
Alignment Buffer reset be followed by a Word Sync Sequence
to ensure proper operation.
Encoder
Each character received from the Input Register or
Phase-Align Buffer is passed to the Encoder logic. This block
interprets each character and any associated control bits, and
outputs a 10-bit transmission character.
Depending on the operational mode, the generated trans-
mission character may be
the 10-bit pre-encoded character accepted in the Input
Register.
the 10-bit equivalent of the 8-bit Data character accepted in
the Input Register.
the 10-bit equivalent of the 8-bit Special Character code
accepted in the Input Register.
the 10-bit equivalent of the C0.7 violation character if a
Phase-Align Buffer overflow or underflow error is present.
a character that is part of the 511-character BIST sequence.
a K28.5 character generated as an individual character or
as part of the 16-character Word Sync Sequence.
Data Encoding
Raw data, as received directly from the Transmit Input
Register, is seldom in a form suitable for transmission across
a serial link. The characters must usually be processed or
transformed to guarantee
a minimum transition density (to allow the receive PLL to
extract a clock from the serial data stream).
a DC-balance in the signaling (to prevent baseline wander).
run-length limits in the serial data (to limit the bandwidth
requirements of the serial link).
the remote receiver a way of determining the correct
character boundaries (framing).
When the Encoder is enabled (ENCBYPx = 1), the characters
transmitted are converted from Data or Special Character
codes to 10-bit transmission characters, using an integrated
8B/10B encoder. When directed to encode the character as a
Special Character code, the encoder uses the Special
Table 1. Input Register Bit Assignments
[7]
Signal Name
TXDx[0] (LSB)
TXDx[1]
TXDx[2]
TXDx[3]
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
TXCTx[0]
TXCTx[1] (MSB)
Unencoded
DINx[0]
DINx[1]
DINx[2]
DINx[3]
DINx[4]
DINx[5]
DINx[6]
DINx[7]
DINx[8]
DINx[9]
Encoded
TXDx[0]
TXDx[1]
TXDx[2]
TXDx[3]
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
TXCTx[0]
TXCTx[1]
Note
7. LSB shifted out first.
[+] Feedback
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| CYV15G0403TB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Serializer |
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| CYV15G0403TB-BGC | 功能描述:電信線路管理 IC 4x Indep Serializer COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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| CYV15G0404DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver with Reclocker |
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