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參數(shù)資料
| 型號： | CYV15G0203TB-BGXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Independent Clock Dual HOTLink II⑩ Serializer |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, LEAD FREE, TBGA-256 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大小： | 307K |
| 代理商： | CYV15G0203TB-BGXC |
CYV15G0203TB
Document #: 38-02105 Rev. *C
Page 9 of 20
Table 1. Operating Speed Settings
The REFCLKx± inputs are differential inputs with each input
internally biased to 1.4V. If the REFCLKx+ input is connected
to a TTL, LVTTL, or LVCMOS clock source, the input signal is
recognized when it passes through the internally biased
reference point. When driven by a single-ended TTL, LVTTL,
or LVCMOS clock source, connect the clock source to either
the true or complement REFCLKx input, and leave the
alternate REFCLKx input open (floating).
When both the REFCLKx+ and REFCLKx– inputs are
connected, the clock source must be a differential clock. This
can either be a differential LVPECL clock that is DC-or
AC-coupled or a differential LVTTL or LVCMOS clock.
By connecting the REFCLKx– input to an external voltage
source, it is possible to adjust the reference point of the
REFCLKx+ input for alternate logic levels. When doing so, it
is necessary to ensure that the input differential crossing point
remains within the parametric range supported by the input.
Serial Output Drivers
The serial output interface drivers use differential Current
Mode Logic (CML) drivers to provide source-matched drivers
for 50
Ω
transmission lines. These drivers accept data from the
Transmit Shifter, which shifts the data out LSB first. These
drivers have signal swings equivalent to that of standard PECL
drivers, and are capable of driving AC-coupled optical
modules or transmission lines.
Transmit Channels Enabled
Each driver can be enabled or disabled separately via the
device configuration interface.
When a driver is disabled via the configuration interface, it is
internally powered down to reduce device power. If both serial
drivers for a channel are in this disabled state, the associated
internal logic for that channel is also powered down. A device
reset (RESET sampled LOW) disables all output drivers.
Note
. When a disabled channel (i.e., both outputs disabled) is
re-enabled:
data on the serial outputs may not meet all timing specifi-
cations for up to 250
μ
s
the state of the phase-align buffer cannot be guaranteed,
and a phase-align reset is required if the phase-align buffer
is used
Device Configuration and Control Interface
The CYV15G0203TB is highly configurable via the configu-
ration interface. The configuration interface allows each
channel to be configured independently.
Table 2 on page 10
lists the configuration latches within the device including the
initialization value of the latches upon the assertion of RESET.
Table 3 on page 11
shows how the latches are mapped in the
device. Each row in the
Table 3
maps to a 4-bit latch bank.
There are 6 such write-only latch banks. When WREN = 0, the
logic value in the DATA[3:0] is latched to the latch bank
specified by the values in ADDR[2:0]. The second column of
Table 3
specifies the channels associated with the corre-
sponding latch bank. For example, the first three latch banks
(0,1 and 2) consist of configuration bits for channel A.
Latch Types
There are two types of latch banks: static (S) and dynamic (D).
Each channel is configured by 2 static and 1 dynamic latch
banks. The S type contain those settings that normally do not
change for a given application, whereas the D type controls
the settings that could change during the application's lifetime.
The first and second rows of each channel (address numbers
0, 1, 5, and 6) are the static control latches. The third row of
latches for each channel (address numbers 2 and 7) are the
dynamic control latches. Address numbers 3 and 4 are internal
test registers.
Static Latch Values
There are some latches in the table that have a static value
(i.e. 1, 0, or X). The latches that have a ‘1’ or ‘0’ must be
configured with their corresponding value each time that their
associated latch bank is configured. The latches that have an
‘X’ are don’t cares and can be configured with any value.
SPDSELx
TXRATEx
REFCLKx±
Frequency
(MHz)
reserved
19.5–40
20–40
40–80
40–75
80–150
Signaling
Rate (Mbps)
LOW
1
0
1
0
1
0
195–400
MID (Open)
400–800
HIGH
800–1500
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYV15G0203TB | Independent Clock Dual HOTLink II Serializer |
| CYV15G0203TB-BGC | Independent Clock Dual HOTLink II Serializer |
| CYV15G0204RB | Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
| CYV15G0204RB-BGC | Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
| CYV15G0204RB-BGXC | Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYV15G0204RB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
| CYV15G0204RB_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Dual HOTLink II Reclocking Deserializer |
| CYV15G0204RB-BGC | 功能描述:視頻 IC 2x Indep Reclockers COM RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CYV15G0204RB-BGXC | 功能描述:IC DESERIAL HOTLINK 256LBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類型:串行 輸出類型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:管件 |
| CYV15G0204TRB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer |
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