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參數(shù)資料
| 型號： | CYV15G0203TB-BGXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Independent Clock Dual HOTLink II⑩ Serializer |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, LEAD FREE, TBGA-256 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大小： | 307K |
| 代理商： | CYV15G0203TB-BGXC |
CYV15G0203TB
Document #: 38-02105 Rev. *C
Page 14 of 20
CYV15G0203TB REFCLKx Switching Characteristics
Over the Operating Range
f
REF
REFCLKx Clock Frequency
t
REFCLK
REFCLKx Period = 1/f
REF
t
REFH
REFCLKx HIGH Time (TXRATEx = 1)(Half Rate)
REFCLKx HIGH Time (TXRATEx = 0)(Full Rate)
t
REFL
REFCLKx LOW Time (TXRATEx = 1)(Half Rate)
REFCLKx LOW Time (TXRATEx = 0)(Full Rate)
t
REFD[18]
REFCLKx Duty Cycle
t
REFR [14, 15, 16, 17]
REFCLKx Rise Time (20%–80%)
t
REFF[14, 15, 16, 17]
REFCLKx Fall Time (20%–80%)
t
TREFDS
Transmit Data Set-up Time to
REFCLKx - Full Rate
(TXRATEx = 0, TXCKSELx
=
1)
Transmit Data Set-up Time to
REFCLKx - Half Rate
(TXRATEx = 1, TXCKSELx
=
1)
t
TREFDH
Transmit Data Hold Time from REFCLKx - Full Rate
(TXRATEx = 0, TXCKSELx
=
1)
Transmit Data Hold Time from REFCLKx - Half Rate
(TXRATEx = 1, TXCKSELx
=
1)
CYV15G0203TB Bus Configuration Write Timing Characteristics
Over the Operating Range
t
DATAH
Bus Configuration Data Hold
t
DATAS
Bus Configuration Data Setup
t
WRENP
Bus Configuration WREN Pulse Width
CYV15G0203TB JTAG Test Clock Characteristics
Over the Operating Range
f
TCLK
JTAG Test Clock Frequency
t
TCLK
JTAG Test Clock Period
CYV15G0203TB Device RESET Characteristics
Over the Operating Range
t
RST
Device RESET Pulse Width
CYV15G0203TB Transmit Serial Outputs and TX PLL Characteristics
Over the Operating Range
Parameter
Description
t
B
Bit Time
t
RISE[14]
CML Output Rise Time 20
80% (CML Test Load)
19.5
6.6
5.9
2.9
[14]
5.9
2.9
[14]
30
150
51.28
MHz
ns
ns
ns
ns
ns
%
ns
ns
ns
70
2
2
2.4
2.3
ns
1.0
ns
1.6
ns
0
ns
ns
ns
10
10
20
MHz
ns
50
30
ns
Condition
Min.
5128
50
100
180
50
100
180
Max.
660
270
500
1000
270
500
1000
Unit
ps
ps
ps
ps
ps
ps
ps
SPDSELx = HIGH
SPDSELx = MID
SPDSELx =LOW
SPDSELx = HIGH
SPDSELx = MID
SPDSELx =LOW
t
FALL[14]
CML Output Fall Time 80
20% (CML Test Load)
CYV15G0203TB AC Electrical Characteristics
(continued)
Parameter
Description
Min.
Max.
Unit
Note
18.cannot be as large as 30%–70%.
REFH
and t
REFL
parameters. This means that at faster character rates the REFCLKx± duty cycle
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYV15G0203TB | Independent Clock Dual HOTLink II Serializer |
| CYV15G0203TB-BGC | Independent Clock Dual HOTLink II Serializer |
| CYV15G0204RB | Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
| CYV15G0204RB-BGC | Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
| CYV15G0204RB-BGXC | Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYV15G0204RB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
| CYV15G0204RB_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Dual HOTLink II Reclocking Deserializer |
| CYV15G0204RB-BGC | 功能描述:視頻 IC 2x Indep Reclockers COM RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CYV15G0204RB-BGXC | 功能描述:IC DESERIAL HOTLINK 256LBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類型:串行 輸出類型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:管件 |
| CYV15G0204TRB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer |
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