- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380227 > CYV15G0203TB-BGXC (CYPRESS SEMICONDUCTOR CORP) Independent Clock Dual HOTLink II⑩ Serializer PDF資料下載
參數(shù)資料
| 型號： | CYV15G0203TB-BGXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Independent Clock Dual HOTLink II⑩ Serializer |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, LEAD FREE, TBGA-256 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大小： | 307K |
| 代理商： | CYV15G0203TB-BGXC |
CYV15G0203TB
Document #: 38-02105 Rev. *C
Page 6 of 20
Pin Definitions
CYV15G0203TB Dual HOTLink II Serializer
Name
Transmit Path Data and Status Signals
TXDA[9:0]
TXDB[9:0]
synchronous,
sampled by the
associated
TXCLKx
↑
or
REFCLKx
↑
[2]
TXERRA
TXERRB
synchronous to
REFCLKx
↑
[3]
,
asynchronous to
transmit channel
enable / disable,
asynchronous to loss
or return of REFCLKx±
I/O Characteristics
Signal Description
LVTTL Input,
Transmit Data Inputs
. TXDx[9:0] data inputs are captured on the rising edge of the
transmit interface clock. The transmit interface clock is selected by the TXCKSELx
latch via the device configuration interface.
LVTTL Output,
Transmit Path Error
. TXERRx is asserted HIGH to indicate detection of a transmit
Phase-Align Buffer underflow or overflow. If an underflow or overflow condition is
detected, TXERRx, for the channel in error, is asserted HIGH and remains asserted
until the transmit Phase-Align Buffer is re-centered with the PABRSTx latch via the
device configuration interface. When TXBISTx = 0, the BIST progress is presented
on the associated TXERRx output. The TXERRx signal pulses HIGH for one
transmit-character clock period to indicate a pass through the BIST sequence once
every 511 character times.
TXERRx is also asserted HIGH, when any of the following conditions is true:
The TXPLL for the associated channel is powered down. This occurs when OE2x
and OE1x for a given channel are both disabled by setting OE2x = 0 and OE1x = 0.
The absence of the REFCLKx± signal.
Transmit Path Clock Signals
REFCLKA±
REFCLKB±
Differential LVPECL or
single-ended
LVTTL input clock
Reference Clock
. REFCLKx± clock inputs are used as the timing references for the
associated transmit PLL. These input clocks may also be selected to clock the
transmit parallel interface. When driven by a single-ended LVCMOS or LVTTL clock
source, connect the clock source to either the true or complement REFCLKx input,
and leave the alternate REFCLKx input open (floating). When driven by an LVPECL
clock source, the clock must be a differential clock, using both inputs.
Transmit Path Input Clock
. When configuration latch TXCKSELx = 0, the associated
TXCLKx input is selected as the character-rate input clock for the TXDB[9:0] input. In
this mode, the TXCLKx input must be frequency-coherent to its associated TXCLKOx
output clock, but may be offset in phase by any amount. Once initialized, TXCLKx is
allowed to drift in phase as much as ±180 degrees. If the input phase of TXCLKx drifts
beyond the handling capacity of the Phase Align Buffer, TXERRx is asserted to
indicate the loss of data, and remains asserted until the Phase Align Buffer is
initialized. The phase of the TXCLKx input clock relative to its associated REFCLKx±
is initialized when the configuration latch PABRSTx is written as 0. When the
associated TXERRx is deasserted, the Phase Align Buffer is initialized and input
characters are correctly captured.
Transmit Clock Output
. TXCLKOx output clock is synthesized by each channel’s
transmit PLL and operates synchronous to the internal transmit character clock.
TXCLKOx operates at either the same frequency as REFCLKx± (TXRATEx = 0), or
at twice the frequency of REFCLKx± (TXRATEx = 1). The transmit clock outputs have
no fixed phase relationship to REFCLKx±.
TXCLKA
TXCLKB
LVTTL Clock Input,
internal pull-down
TXCLKOA
TXCLKOB
LVTTL Output
Device Control Signals
RESET
LVTTL Input,
asynchronous,
internal pull-up
Asynchronous Device Reset
. RESET initializes all state machines, counters, and
configuration latches in the device to a known state. RESET must be asserted LOW
for a minimum pulse width. When the reset is removed, all state machines, counters
and configuration latches are at an initial state. As per the JTAG specifications the
device RESET cannot reset the JTAG controller. Therefore, the JTAG controller has
to be reset separately. Refer to
“JTAG Support” on page 10
for the methods to reset
the JTAG state machine. See
Table 2 on page 10
for the initialize values of the device
configuration latches.
Notes
2. When REFCLKx± is configured for half-rate operation, these inputs are sampled relative to both the rising and falling edges of the associated REFCLKx±.
3. When REFCLKx± is configured for half-rate operation, these outputs are presented relative to both the rising and falling edges of the associated REFCLKx±.
[+] Feedback
相關PDF資料 |
PDF描述 |
|---|---|
| CYV15G0203TB | Independent Clock Dual HOTLink II Serializer |
| CYV15G0203TB-BGC | Independent Clock Dual HOTLink II Serializer |
| CYV15G0204RB | Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
| CYV15G0204RB-BGC | Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
| CYV15G0204RB-BGXC | Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CYV15G0204RB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
| CYV15G0204RB_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Dual HOTLink II Reclocking Deserializer |
| CYV15G0204RB-BGC | 功能描述:視頻 IC 2x Indep Reclockers COM RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CYV15G0204RB-BGXC | 功能描述:IC DESERIAL HOTLINK 256LBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類型:串行 輸出類型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應商設備封裝:64-TQFP-EP（10x10） 包裝:管件 |
| CYV15G0204TRB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer |
發(fā)布緊急采購，3分鐘左右您將得到回復。