參數(shù)資料
型號(hào)： CYV15G0104TRB-BGXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Independent Clock HOTLink II⑩ Serializer and Reclocking Deserializer
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, 1.57 MM HEIGHT, LEAD FREE, BGA-256
文件頁(yè)數(shù)： 10/28頁(yè)
文件大?。?/td> 371K
代理商： CYV15G0104TRB-BGXC
CYV15G0104TRB
Document #: 38-02100 Rev. *C
Page 10 of 28
CYV15G0104TRB HOTLink II Operation
The CYV15G0104TRB is a highly configurable, independent
clocking device designed to support reliable transfer of large
quantities of digital video data, using high-speed serial links
from multiple sources to multiple destinations.
CYV15G0104TRB Transmit Data Path
Input Register
The parallel input bus TXDB[9:0] can be clocked in using
TXCLKB (TXCKSELB = 0) or REFCLKB (TXCKSELB = 1).
Phase-Align Buffer
Data from the Input Register is passed to the Phase-Align
Buffer, when the TXDB[9:0] input register is clocked using
TXCLKBA (TXCKSELB = 0) or when REFCLKB is a half-rate
clock (TXCKSELB = 1 and TXRATEB = 1). When the
TXDB[9:0] input register is clocked using REFCLKB±
(TXCKSELA = 1) and REFCLKB± is a full-rate clock
(TXRATEB = 0), the associated Phase Alignment Buffer in the
transmit path is bypassed. These buffers are used to absorb
clock phase differences between the TXCLKB input clock and
the internal character clock for that channel.
Once initialized, TXCLKB is allowed to drift in phase as much
as ±180 degrees. If the input phase of TXCLKB drifts beyond
the handling capacity of the Phase Align Buffer, TXERRB is
asserted to indicate the loss of data, and remains asserted
until the Phase Align Buffer is initialized. The phase of
TXCLKB relative to its internal character rate clock is initialized
when the configuration latch PABRSTB is written as 0. When
the associated TXERRB is deasserted, the Phase Align Buffer
is initialized and input characters are correctly captured.
If the phase offset, between the initialized location of the input
clock and REFCLKB, exceeds the skew handling capabilities
of the Phase-Align Buffer, an error is reported on that
channel’s TXERRB output. This output indicates an error
continuously until the Phase-Align Buffer for that channel is
reset. While the error remains active, the transmitter for that
channel outputs a continuous “1001111000” character to
indicate to the remote receiver that an error condition is
present in the link.
Transmit BIST
The transmit channel contains an internal pattern generator
that can be used to validate both the link and device operation.
This generator is enabled by the TXBISTB latch via the device
configuration interface. When enabled, a register in the
transmit channel becomes a signature pattern generator by
logically converting to a Linear Feedback Shift Register
(LFSR). This LFSR generates a 511-character sequence. This
provides a predictable yet pseudo-random sequence that can
be matched to an identical LFSR in the attached Receiver(s).
A device reset (RESET sampled LOW) presets the BIST
Enable Latches to disable BIST on all channels.
All data present at the TXDB[9:0] inputs are ignored when
BIST is active on that channel.
Transmit PLL Clock Multiplier
The Transmit PLL Clock Multiplier accepts a character-rate or
half-character-rate external clock at the REFCLKB± input, and
that clock is multiplied by 10 or 20 (as selected by TXRATEB)
to generate a bit-rate clock for use by the transmit shifter. It
also provides a character-rate clock used by the transmit
paths, and outputs this character rate clock as TXCLKOB.
The clock multiplier PLL can accept a REFCLKB± input
between 19.5 MHz and 150 MHz, however, this clock range is
limited by the operating mode of the CYV15G0104TRB clock
multiplier (TXRATEB) and by the level on the SPDSELB input.
SPDSELB is a 3-level select
[4]
input that selects one of three
operating ranges for the serial data outputs of the transmit
channel. The operating serial signaling-rate and allowable
range of REFCLKB± frequencies are listed in
Table 1
.
Table 1. Operating Speed Settings
The REFCLKB± inputs are differential inputs with each input
internally biased to 1.4V. If the REFCLKB+ input is connected
to a TTL, LVTTL, or LVCMOS clock source, the input signal is
recognized when it passes through the internally biased
reference point. When driven by a single-ended TTL, LVTTL,
or LVCMOS clock source, connect the clock source to either
TDI
LVTTL Input,
internal pull-up
LVTTL Input,
internal pull-up
Test Data In
. JTAG data input port.
TRST
JTAG reset signal
. When asserted (LOW), this input asynchronously resets the JTAG
test access port controller.
Power
V
CC
GND
+3.3V Power
.
Signal and Power Ground for all internal circuits
.
Pin Definitions
(continued)
CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer
Name
I/O Characteristics
Signal Description
SPDSELB
TXRATEB
REFCLKB±
Frequency
(MHz)
reserved
19.5–40
20–40
40–80
40–75
80–150
Signaling
Rate (Mbps)
LOW
1
0
1
0
1
0
195–400
MID (Open)
400–800
HIGH
800–1500
[+] Feedback
相關(guān)PDF資料
PDF描述
CYV15G0203TB_07 Independent Clock Dual HOTLink II⑩ Serializer
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CYV15G0203TB Independent Clock Dual HOTLink II Serializer
CYV15G0203TB-BGC Independent Clock Dual HOTLink II Serializer
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CYV15G0201DXB 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Dual-channel HOTLink II⑩ Transceiver
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CYV15G0201DXB-BBI 制造商:Cypress Semiconductor 功能描述:
CYV15G0201DXB-BBXC 功能描述:電信線路管理 IC Dual Ch Video COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
CYV15G0201DXB-BBXI 功能描述:電信線路管理 IC Dual Ch Video IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
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