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參數(shù)資料
| 型號： | CYS25G0101DX-ATXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET OC-48 Transceiver |
| 中文描述： | TRANSCEIVER, PQFP120 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-120 |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 291K |
| 代理商： | CYS25G0101DX-ATXI |
CYS25G0101DX
Document Number: 38-02009 Rev. *K
Page 3 of 17
Clocking
The source clock for the transmit data path is selectable from either the recovered clock or an external BITS (Building Integrated
Timing Source) reference clock. The low jitter of the CDR PLL allows loop timed operation of the transmit data path meeting all Bellcore
and ITU jitter requirements.
Multiple loopback and loop through modes are available for both diagnostic and normal operation. For systems containing redundant
SONET rings that are maintained in standby, the CYS25G0101DX may also be dynamically powered down to conserve system power.
SONET Data
Processor
Serial Data
Optical
XCVR
RD+
RD–
SD
TD–
TD+
IN+
IN–
SD
OUT–
OUT+
Serial Data
CYS25G0101DX
BITS Time
Reference
155.52 MHz
REFCLK
±
TXD[15:0]
TXCLKI
FIFO_RST
FIFO_ERR
TXCLKO
RXD[15:0]
RXCLK
2
LOOPTIME
DIAGLOOP
LOOPA
LINELOOP
RESET
PWRDN
LOCKREF
LFI
16
16
Transmit Data
Interface
Receive Data
Interface
Data & Clock
Direction
Control
Status and
System
Control
Host Bus
Interface
S
Optical
Fiber Links
Figure 1. CYS25G0101DX System Connections
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