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參數(shù)資料
| 型號： | CYS25G0101DX-ATXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET OC-48 Transceiver |
| 中文描述： | TRANSCEIVER, PQFP120 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-120 |
| 文件頁數(shù)： | 11/17頁 |
| 文件大?。?/td> | 291K |
| 代理商： | CYS25G0101DX-ATXI |
CYS25G0101DX
Document Number: 38-02009 Rev. *K
Page 11 of 17
AC Specifications
Table 6. AC Specifications—Parallel Interface
Parameter
Description
Min
Max
Unit
t
TS
t
TXCLKI
t
TXCLKID
t
TXCLKIR
t
TXCLKIF
t
TXDS
t
TXDH
t
TOS
t
TXCLKO
t
TXCLKOD
t
TXCLKOR
t
TXCLKOF
t
RS
t
RXCLK
t
RXCLKD
t
RXCLKR
t
RXCLKF
t
RXDS
t
RXDH
t
RXPD
TXCLKI Frequency (must be frequency coherent to REFCLK)
154.5
156.5
MHz
TXCLKI Period
6.38
6.47
ns
TXCLKI Duty Cycle
40
60
%
TXCLKi Rise Time
0.3
1.5
ns
TXCLKi Fall Time
Write Data Setup to
↑
of TXCLKI
Write Data Hold from
↑
of TXCLKI
0.3
1.5
ns
1.5
ns
0.5
ns
TXCLKO Frequency
154.5
156.5
MHz
TXCLKO Period
6.38
6.47
ns
TXCLKO Duty Cycle
43
57
%
TXCLKO Rise Time
0.3
1.5
ns
TXCLKO Fall Time
0.3
1.5
ns
RXCLK Frequency
154.5
156.5
MHz
RXCLK Period
6.38
6.47
ns
RXCLK Duty Cycle
RXCLK Rise Time
[6]
RXCLK Fall Time
[6]
Recovered Data Setup with reference to
↑
of RXCLK
Recovered Data Hold with reference to
↑
of RXCLK
43
57
%
0.3
1.5
ns
0.3
1.5
ns
2.2
ns
2.2
ns
Valid Propagation Delay
–1.0
1.0
ns
Table 7. AC Specifications—REFCLK
The AC Specifications—REFCLK follow.
[7]
Parameter
Description
Min
Max
Unit
t
REF
t
REFP
t
REFD
t
REFT
t
REFR
t
REFF
REFCLK Input Frequency
154.5
156.5
MHz
REFCLK Period
6.38
6.47
ns
REFCLK Duty Cycle
REFCLK Frequency Tolerance — (relative to received serial data)
[8]
35
65
%
–100
+100
ppm
REFCLK Rise Time
0.3
1.5
ns
REFCLK Fall Time
0.3
1.5
ns
Table 8. AC Specifications–CML Serial Outputs
Parameter
Description
Min
Typical
Max
Unit
t
RISE
t
FALL
CML Output Rise Time (20–80%, 100
balanced load)
CML Output Fall Time (80–20%, 100
balanced load)
60
170
ps
60
170
ps
Notes
6. RXCLk rise time and fall times are measured at the 20 to 80 percentile region of the rising and falling edge of the clock signal.
7. The 155.52 MHz Reference Clock Phase Noise Limits for the CYS25G0101DX are shown in
Figure 6
.
8. +20 ppm is required to meet the SONET output frequency specification.
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