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參數(shù)資料
| 型號(hào)： | CYS25G0101DX-ATXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET OC-48 Transceiver |
| 中文描述： | TRANSCEIVER, PQFP120 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-120 |
| 文件頁數(shù)： | 8/17頁 |
| 文件大?。?/td> | 291K |
| 代理商： | CYS25G0101DX-ATXC |
CYS25G0101DX
Document Number: 38-02009 Rev. *K
Page 8 of 17
Power Down Mode
CYS25G0101DX provides a global power down signal PWRDN.
When LOW, this signal powers down the entire device to a
minimal power dissipation state. RESET and FIFO_RST signals
should be asserted LOW along with PWRDN signal to ensure
low power dissipation.
LVPECL Compliance
The CYS25G0101DX HSTL parallel I/O can be configured to
LVPECL compliance with slight termination modifications. On
the transmit side of the transceiver, the TXD[15:0] and TXCLKI
are made LVPECL compliant by setting V
REF
(reference voltage
of a LVPECL signal) to V
CC
– 1.33V. To emulate an LVPECL
signal on the receiver side, set the VDDQ to 3.3V and the trans-
mission lines needs to be terminated with the Thévenin equiv-
alent of Z
ο
at LVPECL ref. The signal is then attenuated using a
series resistor at the driver end of the line to reduce the 3.3V
swing level to an LVPECL swing level (see
Figure 10
). This
circuit needs to be used on all 16 RXD[15:0] pins, TXCLKO, and
RXCLK. The voltage divider is calculated assuming the system
is built with 50
transmission lines.
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
V
CC
Supply Voltage to Ground Potential........–0.5V to +4.2V
V
DDQ
Supply Voltage to Ground Potential......–0.5V to +4.2V
DC Voltage Applied to HSTL Outputs
in High Z State.....................................–0.5V to V
DDQ
+ 0.5V
DC Voltage Applied to Other Outputs
in High Z State.......................................–0.5V to V
CC
+ 0.5V
Output Current into LVTTL Outputs (LOW) .................30 mA
Table 1. DC Specifications—LVTTL
DC Input Voltage ................................... –0.5V to V
CC
+ 0.5V
Static Discharge Voltage........................................... > 1100V
(MIL-STD-883, Method 3015)
Latch up Current.....................................................> 200 mA
Power Up Requirements
Power supply sequencing is not required if you are configuring
V
DDQ
=3.3V and all power supplies pins are connected to the
same 3.3V power supply.
Power supply sequencing is required if you are configuring
V
DDQ
=1.5V. Power is applied in the following sequence: V
CC
(3.3) followed by V
DDQ
(1.5). Power supply ramping may occur
simultaneously as long as the V
CC
/V
DDQ
relationship is
maintained.
Operating Range
Range
Ambient
Temperature
V
DDQ
V
CC
Commercial
0°C to +70°C
–40°C to +85°C 1.4V to 1.6V
[4]
1.4V to 1.6V
[4]
3.3V ± 10%
Industrial
3.3V ± 10%
Parameter
Description
Test Conditions
Min
Max
Unit
LVTTL Outputs
V
OHT
V
OLT
I
OS
LVTTL Inputs
Output HIGH Voltage
V
CC
= Min, I
OH
= –10.0 mA
V
CC
= Min, I
OL
= 10.0 mA
V
OUT
= 0V
2.4
V
Output LOW Voltage
0.4
V
Output Short Circuit Current
–20
–90
mA
V
IHT
V
ILT
I
IHT
I
ILT
Capacitance
Input HIGH Voltage
Low = 2.1V, High = V
CC
+ 0.5V
Low = –3.0V, High = 0.8
2.1
V
CC
– 0.3
0.8
V
Input LOW Voltage
–0.3
V
Input HIGH Current
V
CC
= Max, V
IN
= V
CC
V
CC
= Max, V
IN
= 0V
50
μ
A
Input LOW Current
–50
μ
A
C
IN
Input Capacitance
V
CC
= Max, at
f
= 1 MHz
5
pF
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