參數(shù)資料
型號(hào)： CYP15G0403DXB-BGXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Independent Clock Quad HOTLink II⑩ Transceiver
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, 1.57 MM HEIGHT, LEAD FREE, BGA-256
文件頁(yè)數(shù)： 12/45頁(yè)
文件大?。?/td> 517K
代理商： CYP15G0403DXB-BGXI
CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
Document #: 38-02065 Rev. *F
Page 12 of 45
PABRST[A..D]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Transmit Clock Phase Alignment Buffer Reset
.
GLEN[11..0]
Global Latch Enable
.
FGLEN[2..0]
Force Global Latch Enable
.
Factory Test Modes
LTEN1
LVTTL input,
internal pull-down
Factory Test 1
. LTEN1 input is for factory testing only. This input may be left as a NO
CONNECT, or GND only.
SCANEN2
LVTTL input,
internal pull-down
Factory Test 2.
SCANEN2 input is for factory testing only. This input may be left as
a NO CONNECT, or GND only.
TMEN3
LVTTL input,
internal pull-down
Factory Test 3
. TMEN3 input is for factory testing only. This input may be left as a
NO CONNECT, or GND only.
Analog I/O
OUTA1±
OUTB1±
OUTC1±
OUTD1±
CML Differential
Output
Primary Differential Serial Data Output
. The OUTx1± PECL-compatible CML
outputs (+3.3V referenced) are capable of driving terminated transmission lines or
standard fiber-optic transmitter modules, and must be AC-coupled for
PECL-compatible connections.
OUTA2±
OUTB2±
OUTC2±
OUTD2±
CML Differential
Output
Secondary Differential Serial Data Output
. The OUTx2± PECL-compatible CML outputs
(+3.3V referenced) are capable of driving terminated transmission lines or standard
fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible connec-
tions.
INA1±
INB1±
INC1±
IND1±
Differential Input
Primary Differential Serial Data Input
. The INx1± input accepts the serial data
stream for deserialization and decoding. The INx1± serial stream is passed to the
receive CDR circuit to extract the data content when INSELx = HIGH.
INA2±
INB2±
INC2±
IND2±
Differential Input
Secondary Differential Serial Data Input
. The INx2± input accepts the serial data
stream for deserialization and decoding. The INx2± serial stream is passed to the
receiver CDR circuit to extract the data content when INSELx = LOW.
JTAG Interface
TMS
LVTTL Input,
internal pull-up
Test Mode Select
. Used to control access to the JTAG Test Modes. If maintained
high for
≥
5 TCLK cycles, the JTAG test controller is reset.
TCLK
LVTTL Input,
internal pull-down
JTAG Test Clock
.
TDO
3-State LVTTL
Output
Test Data Out
. JTAG data output buffer. High-Z while JTAG test mode is not selected.
TDI
LVTTL Input,
internal pull-up
Test Data In
. JTAG data input port.
TRST
LVTTL Input,
internal pull-up
JTAG reset signal
. When asserted (LOW), this input asynchronously resets the
JTAG test access port controller.
Power
V
CC
GND
+3.3V Power
.
Signal and Power Ground for all internal circuits
.
Pin Descriptions
(continued)
CYP(V)(W)15G0403DXB Quad HOTLink II Transceiver
Name
I/O Characteristics
Signal Description
[+] Feedback
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