參數(shù)資料
型號(hào)： CYP15G0403DXB-BGC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Independent Clock Quad HOTLink II⑩ Transceiver
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, 1.57 MM HEIGHT, BGA-256
文件頁(yè)數(shù)： 30/45頁(yè)
文件大?。?/td> 517K
代理商： CYP15G0403DXB-BGC
CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
Document #: 38-02065 Rev. *F
Page 30 of 45
t
REFF[20, 21, 22, 23]
t
TREFDS
REFCLKx Fall Time (20%–80%)
Transmit Data Set-up Time to
REFCLKx - Full Rate
(TXRATEx = 0, TXCKSELx
=
1)
Transmit Data Set-up Time to
REFCLKx - Half Rate
(TXRATEx = 1, TXCKSELx
=
1)
Transmit Data Hold Time from REFCLKx - Full Rate
(TXRATEx = 0, TXCKSELx
=
1)
Transmit Data Hold Time from REFCLKx - Half Rate
(TXRATEx = 1, TXCKSELx
=
1)
Receive Data Access Time to
REFCLKx (RXCKSELx
=
1)
Receive Data Valid Time Window (RXCKSELx
=
1)
Received Data Valid Time to RXCLK when RXCKSELx
=
1
(TXRATEx = 0, RXRATEx = 0)
Received Data Valid Time to RXCLK when RXCKSELx
=
1
(TXRATEx = 0, RXRATEx = 1)
Received Data Valid Time to RXCLK when RXCKSELx
=
1
(TXRATEx = 1)
Received Data Valid Time from RXCLK when RXCKSELx
=
1
(TXRATEx = 0, RXRATEx = 0)
Received Data Valid Time from RXCLK when RXCKSELx
=
1
(TXRATEx = 0, RXRATEx = 1)
Received Data Valid Time from RXCLK when RXCKSELx
=
1
(TXRATEx = 1)
REFCLKx Frequency Referenced to Received Clock Period
CYP(V)(W)15G0403DXB Bus Configuration Write Timing Characteristics
Over the Operating Range
t
DATAH
Bus Configuration Data Hold
t
DATAS
Bus Configuration Data Set-up
t
WRENP
Bus Configuration WREN Pulse Width
CYP(V)(W)15G0403DXB JTAG Test Clock Characteristics
Over the Operating Range
f
TCLK
JTAG Test Clock Frequency
t
TCLK
JTAG Test Clock Period
CYP(V)(W)15G0403DXB Device RESET Characteristics
Over the Operating Range
t
RST
Device RESET Pulse Width
CYP(V)(W)15G0403DXB Transmit Serial Outputs and TX PLL Characteristics
Over the Operating Range
Parameter
Description
t
B
Bit Time
2
ns
ns
2.4
2.3
ns
t
TREFDH
1.0
ns
1.6
ns
t
RREFDA
t
RREFDW
t
REFxDV–
9.7
[28]
ns
ns
ns
10UI – 5.8
10UI
[25]
– 6.16
5UI – 2.53
[29]
ns
10UI – 5.86
[29]
ns
t
REFxDV+
1.4
ns
5UI
– 1.83
[29]
ns
1.0
[29]
ns
t
REFRX[30]
–0.15
+0.15
%
0
10
10
ns
ns
ns
20
MHz
ns
50
30
ns
Condition
Min.
5128
Max.
666
Unit
ps
Notes
28.Since this timing parameter is greater than the minimum time period of REFCLK it sets an upper limit to the frequency in which REFCLKx can be used to clock
the receive data out of the output register. For predictable timing, users can use this parameter only if REFCLK period is greater than sum of t
and set-up
time of the upstream device. When this condition is not true, RXCLKx± (a buffered or divided version of REFCLK when RXCKSELx = 1) could be used to clock
the receive data out of the device.
29.Measured using a 50% duty cycle reference clock.
30.REFCLKx has no phase or frequency relationship with the recovered clock and only acts as a centering reference to reduce clock synchronization time. REFCLKx
must be within ±1500 ppm (±0.15%) of the remote transmitter’s PLL reference (REFCLKx) frequency. Although transmitting to a HOTLink II receiver channel
necessitates the frequency difference between the transmitter and receiver reference clocks to be within ±1500 ppm, the stability of the crystal needs to be
within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard. For example, to be IEEE 802.3z
Gigabit Ethernet compliant, the frequency stability of the crystal needs to be within ±100 ppm.l.
CYP(V)(W)15G0403DXB AC Electrical Characteristics
(continued)
Parameter
Description
Min.
Max
Unit
[+] Feedback
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