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參數(shù)資料
| 型號： | CYP15G0403DXB-BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, BGA-256 |
| 文件頁數(shù)： | 22/45頁 |
| 文件大?。?/td> | 517K |
| 代理商： | CYP15G0403DXB-BGC |
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CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
Document #: 38-02065 Rev. *F
Page 22 of 45
ENCBYPA
ENCBYPB
ENCBYPC
ENCBYPD
TXCKSELA
TXCKSELB
TXCKSELC
TXCKSELD
Transmit Encoder Bypassed
. The initialization value of the ENCBYPx latch = 1. ENCBYPx selects if the
Transmit Encoder is enabled or bypassed. When ENCBYPx = 1, the Transmit encoder is enabled. When
ENCBYPx = 0, the Transmit Encoder is bypassed and raw 10-bit characters are transmitted.
Transmit Clock Select
. The initialization value of the TXCKSELx latch = 1. TXCKSELx selects the clock
source used to write data into the Transmit Input Register. When TXCKSELx = 1, the associated input register,
TXDx[7:0] and TXCTx[1:0], is clocked by REFCLKx
↑.
In this mode, the phase alignment buffer in the transmit
path is bypassed. When TXCKSELx = 0, the associated TXCLKx
↑
is used to clock in the input registers,
TXDx[7:0] and TXCTx[1:0].
Transmit PLL Clock Rate Select
. The initialization value of the TXRATEx latch = 0. TXRATEx is used to
select the clock multiplier for the Transmit PLL. When TXRATEx = 0, each transmit PLL multiples the
associated REFCLKx± input by 10 to generate the serial bit-rate clock. When TXRATEx = 0, the TXCLKOx
output clocks are full-rate clocks and follow the frequency and duty cycle of the associated REFCLKx± input.
When TXRATEx = 1, each Transmit PLL multiplies the associated REFCLKx± input by 20 to generate the
serial bit-rate clock. When TXRATEx = 1, the TXCLKOx output clocks are twice the frequency rate of the
REFCLKx± input. When TXCKSELx = 1 and TXRATEx = 1, the Transmit Data Inputs are captured using both
the rising and falling edges of REFCLKx. TXRATEx = 1 and SPDSELx is LOW, is an invalid state and this
combination is reserved.
Reframe Enable
. The initialization value of the RFENx latch = 1. RFENx selects if the receiver framer is
enabled or disabled. When RFENx = 1, the associated channel’s framer is enabled to frame per the presently
enabled framing mode and selected framing character. When RFENx = 0, the associated channel’s framer is
disabled, and no received bits alters the frame offset.
Receive Channel Enable
. The initialization value of the RXPLLPDx latch = 0. RXPLLPDx selects if the
associated receive channel is enabled or powered-down. When RXPLLPDx = 0, the associated PLL and
analog circuitry is powered-down. When RXPLLPDx = 1, the associated PLL and analog circuitry is enabled.
TXRATEA
TXRATEB
TXRATEC
TXRATED
RFENA
RFENB
RFENC
RFEND
RXPLLPDA
RXPLLPDB
RXPLLPDC
RXPLLPDD
RXBISTA
RXBISTB
RXBISTC
RXBISTD
TXBISTA
TXBISTB
TXBISTC
TXBISTD
OE2A
OE2B
OE2C
OE2D
Receive Bist Disabled
. The initialization value of the RXBISTx latch = 1. RXBISTx selects if receive BIST is
disabled or enabled. When RXBISTx = 1, the receiver BIST function is disabled. When RXBISTx = 0, the
receive BIST function is enabled.
Transmit Bist Disabled
. The initialization value of the TXBISTx latch = 1. TXBISTx selects if the transmit
BIST is disabled or enabled. When TXBISTx = 1, the transmit BIST function is disabled. When TXBISTx = 0,
the transmit BIST function is enabled.
Secondary Differential Serial Data Output Driver Enable
. The initialization value of the OE2x latch = 0.
OE2x selects if the OUT2± secondary differential output drivers are enabled or disabled. When OE2x = 1, the
associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter. When
OE2x = 0, the associated serial data output driver is disabled. When a driver is disabled via the configuration
interface, it is internally powered down to reduce device power. If both serial drivers for a channel are in this
disabled state, the associated internal logic for that channel is also powered down. A device reset (RESET
sampled LOW) disables all output drivers.
Primary Differential Serial Data Output Driver Enable
. The initialization value of the OE1x latch = 0. OE1x
selects if the OUT1± primary differential output drivers are enabled or disabled. When OE1x = 1, the associated
serial data output driver is enabled allowing data to be transmitted from the transmit shifter. When OE1x = 0,
the associated serial data output driver is disabled. When a driver is disabled via the configuration interface,
it is internally powered down to reduce device power. If both serial drivers for a channel are in this disabled
state, the associated internal logic for that channel is also powered down. A device reset (RESET sampled
LOW) disables all output drivers.
Transmit Clock Phase Alignment Buffer Reset
. The initialization value of the PABRSTx latch = 1. The
PABRSTx is used to re-center the Transmit Phase Align Buffer. When the configuration latch PABRSTx is
written as a 0, the phase of the TXCLKx input clock relative to its associated REFCLKx+/- is initialized.
PABRST is an asynchronous input, but is sampled by each TXCLKx
↑
to synchronize it to the internal clock
domain. PABRSTx is a self clearing latch. This eliminates the requirement of writing a 1 to complete the
initialization of the Phase Alignment Buffer.
OE1A
OE1B
OE1C
OE1D
PABRSTA
PABRSTB
PABRSTC
PABRSTD
Table 9. Device Configuration and Control Latch Descriptions
(continued)
Name
Signal Description
[+] Feedback
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| CYW15G0403DXB-BGXC | Independent Clock Quad HOTLink II⑩ Transceiver |
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| CYP15G0403DXB-BGXC | Independent Clock Quad HOTLink II⑩ Transceiver |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0403DXB-BGI | 功能描述:電信線路管理 IC Quad Indep Channel XCVR IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0403DXB-BGXC | 功能描述:電信線路管理 IC Quad Indep Ch HOTLink II XCVR RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0403DXB-BGXI | 功能描述:電信線路管理 IC Ind. Clock Quad HOTLink II Xcvr RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G04K100V1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Physical Layer Devices |
| CYP7C1048AC | 制造商:Cypress Semiconductor 功能描述: |
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