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| 型號： | CYP15G0403DXB-BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, BGA-256 |
| 文件頁數(shù)： | 16/45頁 |
| 文件大?。?/td> | 517K |
| 代理商： | CYP15G0403DXB-BGC |
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CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
Document #: 38-02065 Rev. *F
Page 16 of 45
Analog Amplitude
While most signal monitors are based on fixed constants, the
analog amplitude level detection is adjustable to allow
operation with highly attenuated signals, or in high-noise
environments. The analog amplitude level detection is set by
the SDASELx latch via device configuration interface. The
SDASELx latch sets the trip point for the detection of a valid
signal at one of three levels, as listed in
Table 5
. This control
input affects the analog monitors for all receive channels.
The Analog Signal Detect monitors are active for the Line
Receiver as selected by the associated INSELx input. When
configured for local loopback, no input receivers are selected,
and the LFIx output for each channel reports only the receive
VCO frequency out-of-range and transition density status of
the associated transmit signal. When local loopback is active,
the associated Analog Signal Detect Monitor is disabled.
Transition Density
The Transition Detection logic checks for the absence of
transitions spanning greater than six transmission characters
(60 bits). If no transitions are present in the data received, the
Detection logic for that channel asserts LFIx.
Range Controls
The CDR circuit includes logic to monitor the frequency of the
PLL Voltage Controlled Oscillator (VCO) used to sample the
incoming data stream. This logic ensures that the VCO
operates at, or near the rate of the incoming data stream for
two primary cases:
when the incoming data stream resumes after a time in
which it has been “missing.”
when the incoming data stream is outside the acceptable
signaling rate range.
To perform this function, the frequency of the RXPLL VCO is
periodically compared to the frequency of the REFCLKx±
input. If the VCO is running at a frequency beyond
±1500 ppm
[30]
as defined by the REFCLKx± frequency, it is
periodically forced to the correct frequency (as defined by
REFCLKx±, SPDSELx, and TXRATEx) and then released in
an attempt to lock to the input data stream.
The sampling and relock period of the Range Control is calcu-
lated as follows: RANGE_CONTROL_ SAMPLING_PERIOD
= (RECOVERED BYTE CLOCK PERIOD) * (4096).
During the time that the Range Control forces the RXPLL VCO
to track REFCLKx±, the LFIx output is asserted LOW. After a
valid serial data stream is applied, it may take up to one
RANGE CONTROL SAMPLING PERIOD before the PLL
locks to the input data stream, after which LFIx should be
HIGH.
Receive Channel Enabled
The CYP(V)(W)15G0403DXB contains four receive channels
that can be independently enabled and disabled. Each
channel can be enabled or disabled separately through the
RXPLLPDx input latch as controlled by the device configu-
ration interface. When the RXPLLPDx latch = 0, the
associated PLL and analog circuitry of the channel is disabled.
Any disabled channel indicates a constant link fault condition
on the LFIx output. When RXPLLPDx = 1, the associated PLL
and receive channel is enabled to receive and decode a serial
stream.
Note
. When a disabled receive channel is reenabled, the
status of the associated LFIx output and data on the parallel
outputs for the associated channel may be indeterminate for
up to 2 ms.
Clock/Data Recovery
The extraction of a bit-rate clock and recovery of bits from each
received serial stream is performed by a separate CDR block
within each receive channel. The clock extraction function is
performed by an integrated PLL that tracks the frequency of
the transitions in the incoming bit stream and align the phase
of the internal bit-rate clock to the transitions in the selected
serial data stream.
Each CDR accepts a character-rate (bit-rate
÷
10) or
half-character-rate (bit-rate
÷
20) reference clock from the
associated REFCLKx± input. This REFCLKx± input is used to
ensure that the VCO (within the CDR) is operating at the
correct frequency (rather than a harmonic of the bit-rate)
reduce PLL acquisition time
limit unlocked frequency excursions of the CDR VCO when
there is no input data present at the selected Serial Line
Receiver.
Regardless of the type of signal present, the CDR attempts to
recover a data stream from it. If the signalling rate of the
recovered data stream is outside the limits set by the range
control monitors, the CDR tracks REFCLKx± instead of the
data stream. Once the CDR output (RXCLK±) frequency
returns back close to REFCLKx± frequency, the CDR input is
switched back to the input data stream. If no data is present at
the selected line receiver, this switching behavior may result
in brief RXCLK± frequency excursions from REFCLKx±.
However, the validity of the input data stream is indicated by
the LFIx output. The frequency of REFCLKx± is required to be
within ±1500 ppm
[30]
of the frequency of the clock that drives
the REFCLKx± input of the
remote
transmitter to ensure a lock
to the incoming data stream.
For systems using multiple or redundant connections, the LFIx
output can be used to select an alternate data stream. When
an LFIx indication is detected, external logic can toggle
selection of the associated INx1± and INx2± input through the
associated INSELx input. When a port switch takes place, it is
necessary for the receive PLL for that channel to reacquire the
Table 5. Analog Amplitude Detect Valid Signal Levels
[8]
SDASEL
00
01
10
11
Typical Signal with Peak Amplitudes Above
Analog Signal Detector is disabled
140 mV p-p differential
280 mV p-p differential
420 mV p-p differential
Note
8. The peak amplitudes listed in this table are for typical waveforms that have generally 3–4 transitions for every ten bits. In a worse case environment the signals
may have a sine-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase
the values in the table above by approximately 100 mV.
[+] Feedback
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| CYW15G0403DXB-BGXC | Independent Clock Quad HOTLink II⑩ Transceiver |
| CYW15G0403DXB-BGXI | Independent Clock Quad HOTLink II⑩ Transceiver |
| CYP15G0403DXB-BGI | Independent Clock Quad HOTLink II⑩ Transceiver |
| CYP15G0403DXB-BGXC | Independent Clock Quad HOTLink II⑩ Transceiver |
| CYP15G0403DXB-BGXI | Independent Clock Quad HOTLink II⑩ Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0403DXB-BGI | 功能描述:電信線路管理 IC Quad Indep Channel XCVR IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0403DXB-BGXC | 功能描述:電信線路管理 IC Quad Indep Ch HOTLink II XCVR RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0403DXB-BGXI | 功能描述:電信線路管理 IC Ind. Clock Quad HOTLink II Xcvr RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G04K100V1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Physical Layer Devices |
| CYP7C1048AC | 制造商:Cypress Semiconductor 功能描述: |
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