參數(shù)資料
型號(hào): CYP15G0401DXB
廠商: Cypress Semiconductor Corp.
英文描述: PREMIUM VGA CABLE W/AUDIO3FT, HD15 & 3.5MM M-M
中文描述: 四HOTLink II收發(fā)器
文件頁數(shù): 36/48頁
文件大?。?/td> 1115K
代理商: CYP15G0401DXB
CYP15G0401DXA
PRELIMINARY
Document #: 38-02002 Rev. *B
Page 36 of 48
CYP15G0401DXA Receive Serial Inputs and CDR PLL Characteristics
Over the Operating Range
Parameter
Description
Min.
Max.
Unit
t
RXLOCK
Receive PLL lock to input data stream (cold start)
10
ms
Receive PLL lock to input data stream
2500
UI
t
RXUNLOCK
t
SA
t
EFW
Receive PLL Unlock Rate
Static Alignment
[17, 25]
Error Free Window
[17, 26, 27]
TBD
TBD
ns
ps
0.75
UI
Capacitance
[17]
Parameter
C
INTTL
C
INPECL
Notes:
25. Static alignment is a measure of the alignment of the Receiver sampling point to the center of a bit. Static alignment is measured by sliding one bit edge in
3,000 nominal transitions until a character error occurs.
26. Receiver UI (Unit Interval) is calculated as 1/(f
*20) (when RXRATE = HIGH) or 1/(f
* 10) (when RXRATE = LOW) if no data is being received, or 1/(f
* 20)
(when RXRATE = HIGH) or 1/(f
* 10) (when RXRATE = LOW) of the remote transmitter if data is being received. In an operating link this is equivalent to t
.
27. Error Free Window is a measure of the time window between bit centers where a transition may occur without causing a bit sampling error. EFW is measured
over the operating range, input jitter
<
50% Dj.
Description
Test Conditions
Max.
7
4
Unit
pF
pF
TTL Input Capacitance
PECL input Capacitance
T
A
= 25
°
C, f
0
= 1 MHz, V
CC
= 3.3V
T
A
= 25
°
C, f
0
= 1 MHz, V
CC
= 3.3V
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