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參數(shù)資料
| 型號(hào)： | CYNSE70032-66BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Network Search Engine |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA272 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, BGA-272 |
| 文件頁數(shù)： | 107/126頁 |
| 文件大?。?/td> | 3333K |
| 代理商： | CYNSE70032-66BGC |
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CYNSE70032
Document #: 38-02042 Rev. *E
Page 107 of 126
15.7
The following explains the SRAM Write operation done via a table(s) of up to eight devices with the following parameters:
TLSZ = 01. The diagram of this table is shown in
Figure 15-9
. The following assumes that SRAM access is getting done through
CYNSE70032 device number 0.
Figure 15-10
and
Figure 15-11
show the timing diagram for the device number 0 and device
number 7, respectively.
Cycle 1A
: The host ASIC applies the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with
DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21]
lines. The host ASIC also supplies SADR[21:19] on CMD[8:6] in this cycle.
Note
. CMD[2] must be set to 0 for SRAM Write,
because burst Writes into the SRAM are not supported.
Cycle 1B
: The host ASIC continues to apply the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the
address, with DQ[20:19] set to 10, to select the SRAM address.
Note
. CMD[2] must be set to 0 for SRAM Write, because burst
Writes into the SRAM are not supported.
Cycle 2
: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70032.
Cycle 3
: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70032.
At the end of cycle 3, a new command can begin. The Write is a pipelined operation; however, the Write cycle appears at the
SRAM bus with the same latency as the Search instruction (as measured from the second cycle of the Write command).
SRAM Write with a Table of up to Eight Devices
cycle
1
CLK2X
CMDV
CMD[1:0]
DQ
Write
Address
ACK
OE_L
WE_L
ALE_L
SADR
Address
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1
Figure 15-8. SRAM Write Access (TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1)
PHS_L
CMD[8:2]
A
B
x
x
0
1
z
z
1
SSV
0
0
SSF
CE_L
1
x
1
0
0
0
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