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參數(shù)資料
| 型號(hào)： | CYM1838 |
| 廠(chǎng)商： | Cypress Semiconductor Corp. |
| 英文描述： | 128K x 32 Static RAM Module(128K x 32 靜態(tài)RAM模塊) |
| 中文描述： | 128K的× 32靜態(tài)RAM模塊（128K的× 32靜態(tài)內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大?。?/td> | 244K |
| 代理商： | CYM1838 |
CYM1838
PRELIMINARY
3
Switching Characteristics
Over the Operating Range
[3]
Parameter
READ CYCLE
Description
1838-20
1838-25
1838-35
Unit
Min.
Max.
Min.
Max.
Min.
Max.
t
RC
t
AA
t
OHA
t
ACS
t
DOE
t
LZOE
t
HZOE
t
LZCS
t
HZCS
WRITE CYCLE
[6]
Read Cycle Time
20
25
35
ns
Address to Data Valid
20
25
35
ns
Data Hold from Address Change
3
3
3
ns
CS LOW to Data Valid
20
25
35
ns
OE LOW to Data Valid
10
12
15
ns
OE LOW to Low Z
0
0
0
ns
OE HIGH to High Z
CS LOW to Low Z
[4]
CS HIGH to High Z
[4,5]
10
10
20
ns
0
0
0
ns
12
15
20
ns
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Write Cycle Time
20
25
35
ns
CS LOW to Write End
15
20
30
ns
Address Set-Up to Write End
15
20
30
ns
Address Hold from Write End
1.5
1.5
1.5
ns
Address Set-Up to Write Start
2.0
2.0
2.0
ns
WE Pulse Width
15
17
25
ns
Data Set-Up to Write End
10
12
15
ns
Data Hold from Write End
2
2
2
ns
WE HIGH to Low Z
WE LOW to High Z
[5]
0
0
0
ns
0
10
0
10
0
15
ns
Switching Waveforms
Notes:
3.
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and 30-pF load capacitance.
At any given temperature and voltage condition, t
HZCS
is less than t
LZCS
for any given device. These parameters are guaranteed by design and not 100%
tested.
t
and t
are specified with C
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured
±
500 mV from steady-state voltage.
The internal write time of the memory is defined by the overlap of CS
LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
WE
is HIGH for read cycle.
Device is continuously selected, CS = V
IL
and OE= V
IL
.
4.
5.
6.
7.
8.
Read Cycle No. 1
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
1838–5
ADDRESS
DATA OUT
[7,8]
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|---|---|
| CYM1838LHG-25C | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:x32 SRAM Module |
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| CYM1838LHG-30C | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:x32 SRAM Module |
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