參數(shù)資料
型號(hào)： CYD18S72V18
廠商： Cypress Semiconductor Corp.
英文描述： FullFlex Synchronous SDR Dual-Port SRAM(FullFlex同步SDR雙端口SRAM)
中文描述： FullFlex器件特別提款權(quán)同步雙端口SRAM（FullFlex器件同步雙端口SRAM的特別提款權(quán)）
文件頁(yè)數(shù)： 14/52頁(yè)
文件大小： 774K
代理商： CYD18S72V18
FullFlex
Document #: 38-06082 Rev. *F
Page 14 of 52
Increment Operation
[1]
Once the address counter is initially loaded with an external
address, the counter can internally increment the address
value and address the entire memory array. Only the
unmasked bits of the counter register are incremented. In
order for a counter bit to change, the corresponding bit in the
mask register must be “1”. If the two least significant bits of the
mask register are “11”, the burst counter will increment by one.
If the two least significant bits are “10”, the burst counter will
increment by two, and if they are “00”, the burst counter will
increment by four. If all unmasked counter bits are incre-
mented to “1” and WRP is deasserted, the next increment will
wrap the counter back to the initially loaded value. The cycle
before the increment that results in all unmasked counter bits
to become “1s”, a counter interrupt flag (CNTINT) is asserted
if the counter is incremented again. This increment will cause
the counter to reach its maximum value and the next increment
will return the counter register to its initial value that was stored
in the mirror register if WRP is deasserted. If WRP is asserted,
the unmasked portion of the counter is filled with “0” instead.
The example shown in
Figure 4
shows an example of the
CYDD36S18V18 device with the mask register loaded with a
mask value of 00007F unmasking the seven least significant
bits. Setting the mask register to this value allows the counter
to access the entire memory space. The address counter is
then loaded with an initial value of 000005 assuming WRP is
deasserted. The masked bits, the seventh address through the
twenty-first address, do not increment in an increment
operation. The counter address will start at address 000005
and will increment its internal address value until it reaches the
mask register value of 00007F. The counter wraps around the
memory block to location 000005 at the next count. CNTINT
is issued when the counter reaches the maximum –1 count.
Hold Operation
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are
needed, or when address is available a few cycles ahead of
data in a shared bus interface.
Retransmit
Retransmit allows repeated access to the same block of
memory without the need to reload the initial address. An
internal mirror register stores the address counter value last
loaded. While RET is asserted low, the counter will continue to
wrap back to the value in the mirror register independent of the
state of WRP.
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW one clock
cycle before an increment operation that results in the
unmasked portion of the counter register being all “1s”. It is
deasserted by counter reset, counter load, mask reset, mask
load, and MRST.
Counting by Two
When the two least significant bits of the mask register are
“10,” the counter increments by two.
Counting by Four
When the two least significant bits of the mask register are
“00”, the counter increments by four.
Mailbox Interrupts
The upper two memory locations can be used for message
passing and permit communications between ports.
Table 9
shows the interrupt operation for both ports. The highest
memory location is the mailbox for the right port and the
maximum address – 1 is the mailbox for the left port.
When one port Writes to the other port’s mailbox, the INT flag
of the port that the mailbox belongs to is asserted LOW. The
INT flag remains asserted until the mailbox location is read by
the other port. When a port reads its mailbox, the INT flag is
deasserted high after one cycle of latency with respect to the
input clock of the port to which the mailbox belongs and is
independent of OE.
Table 9
shows that in order to set the INT
R
flag, a Write
operation by the left port to address 1FFFFF will assert INT
R
LOW. A valid Read of the 1FFFFF location by the right port will
reset INT
R
HIGH after one cycle of latency with respect to the
right port’s clock. At least one byte enable has to be activated
to set or reset the mailbox interrupt.
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