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參數(shù)資料
| 型號： | CY8C27666-SPPXC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | PSoC⑩ Mixed Signal Array |
| 中文描述： | ⑩的PSoC混合信號陣列 |
| 文件頁數(shù)： | 33/39頁 |
| 文件大?。?/td> | 610K |
| 代理商： | CY8C27666-SPPXC |
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June 1, 2004
Document No. 38-12019 Rev. *B
33
CY8C27x66 Preliminary Data Sheet
3. Electrical Specifications
3.4.8
AC I
2
C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
≤
T
A
≤
85
°
C, or 3.0V to 3.6V and -40
°
C
≤
T
A
≤
85
°
C, respectively. Typical parameters apply to 5V and 3.3V at 25
°
C and
are for design guidance only or unless otherwise specified.
Figure 3-9. Definition for Timing for Fast/Standard Mode on the I
2
C Bus
Table 3-26: AC Characteristics of the I
2
C SDA and SCL Pins
Symbol
F
SCLI2C
T
HDSTAI2C
Description
Standard Mode
Min
Fast Mode
Min
Units
kHz
Notes
Max
Max
SCL Clock Frequency
0
100
0
400
Hold Time (repeated) START Condition. After this
period, the first clock pulse is generated.
LOW Period of the SCL Clock
4.0
–
0.6
–
μ
s
T
LOWI2C
T
HIGHI2C
T
SUSTAI2C
T
HDDATI2C
T
SUDATI2C
T
SUSTOI2C
T
BUFI2C
T
SPI2C
4.7
–
1.3
–
μ
s
μ
s
μ
s
μ
s
ns
HIGH Period of the SCL Clock
4.0
–
0.6
–
Set-up Time for a Repeated START Condition
4.7
–
0.6
–
Data Hold Time
0
–
0
–
Data Set-up Time
250
–
100
a
0.6
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system but the requirement t
SU;DAT
≥
250 ns must then be met. This will automatically be
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line t
rmax
+ t
SU;DAT
= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
–
Set-up Time for STOP Condition
4.0
–
–
μ
s
μ
s
ns
Bus Free Time Between a STOP and START Condition 4.7
–
1.3
–
Pulse Width of spikes are suppressed by the input fil-
ter.
–
–
0
50
SDA
SCL
S
Sr
S
P
T
BUFI2C
T
SPI2C
T
HDSTAI2C
T
SUSTOI2C
T
SUSTAI2C
T
LOWI2C
T
HIGHI2C
T
HDDATI2C
T
HDSTAI2C
T
SUDATI2C
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY8C28000-24PVXI | 制造商:Cypress Semiconductor 功能描述: |
| CY8C28243-24PVXI | 功能描述:可編程片上系統(tǒng) - PSoC PSoC Programmable System-on-Chip RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:67 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT |
| CY8C28243-24PVXIT | 功能描述:可編程片上系統(tǒng) - PSoC 16 I/O 16K FLASH 1K SRAM RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:67 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT |
| CY8C28403-24PVXI | 功能描述:可編程片上系統(tǒng) - PSoC PSoC Programmable System-on-Chip RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:67 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT |
| CY8C28403-24PVXIT | 功能描述:可編程片上系統(tǒng) - PSoC PSoC Programmable System-on-Chip RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:67 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT |
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