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| 型號(hào)： | CY8C27143-24PXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | PSoC Mixed Signal Array |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PDIP8 |
| 封裝： | 0.300 INCH, LEAD FREE, PLASTIC, DIP-8 |
| 文件頁(yè)數(shù)： | 32/44頁(yè) |
| 文件大?。?/td> | 542K |
| 代理商： | CY8C27143-24PXI |
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August 3, 2004
Document No. 38-12012 Rev. *I
32
CY8C27x43 Final Data Sheet
3. Electrical Specifications
3.4.4
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
≤
T
A
≤
85
°
C, or 3.0V to 3.6V and -40
°
C
≤
T
A
≤
85
°
C, respectively. Typical parameters apply to 5V and 3.3V at 25
°
C and
are for design guidance only.
Table 3-22. AC Digital Block Specifications
Function
Description
Min
Typ
Max
Units
Notes
All
Functions
Maximum Block Clocking Frequency (> 4.75V)
49.2
4.75V < Vdd < 5.25V.
Maximum Block Clocking Frequency (< 4.75V)
24.6
3.0V < Vdd < 4.75V.
Timer
Capture Pulse Width
50
a
a. 50 ns mnimuminput pulse width is based on the input synchronizers running at 24 MHz (42 ns nomnal period).
b. Refer to the
Ordering Informationchapter on page42
.
–
–
ns
Maximum Frequency, No Capture
–
–
49.2
MHz
4.75V < Vdd < 5.25V.
Maximum Frequency, With Capture
–
–
24.6
MHz
Counter
Enable Pulse Width
50
a
–
–
ns
Maximum Frequency, No Enable Input
–
–
49.2
MHz
4.75V < Vdd < 5.25V.
Maximum Frequency, Enable Input
–
–
24.6
MHz
Dead Band
Kill Pulse Width:
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
50
a
–
–
ns
Disable Mode
50
a
–
–
ns
Maximum Frequency
–
–
49.2
MHz
4.75V < Vdd < 5.25V.
CRCPRS
(PRS Mode)
Maximum Input Clock Frequency
–
–
49.2
MHz
4.75V < Vdd < 5.25V.
CRCPRS
(CRC Mode)
Maximum Input Clock Frequency
–
–
24.6
MHz
SPIM
Maximum Input Clock Frequency
–
–
8.2
MHz
Maximum data rate at 4.1 MHz due to 2 x over
clocking.
SPIS
Maximum Input Clock Frequency
–
–
4.1
ns
Width of SS_ Negated Between Transmissions
50
a
–
–
ns
Transmitter
Maximum Input Clock Frequency
b
Silicon A
Silicon B
–
–
–
–
16.4
24.6
MHz
MHz
Maximum data rate at 2.05 MHz due to 8 x over
clocking.
Maximum data rate at 3.08 MHz due to 8 x over
clocking.
Receiver
Maximum Input Clock Frequency
b
Silicon A
Silicon B
–
–
–
–
16.4
24.6
MHz
MHz
Maximum data rate at 2.05 MHz due to 8 x over
clocking.
Maximum data rate at 3.08 MHz due to 8 x over
clocking.
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