參數(shù)資料
型號(hào)： CY8C27143-24PXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 外設(shè)及接口
英文描述： PSoC Mixed Signal Array
中文描述： MULTIFUNCTION PERIPHERAL, PDIP8
封裝： 0.300 INCH, LEAD FREE, PLASTIC, DIP-8
文件頁數(shù)： 22/44頁
文件大?。?/td> 542K
代理商： CY8C27143-24PXI
August 3, 2004
Document No. 38-12012 Rev. *I
22
CY8C27x43 Final Data Sheet
3. Electrical Specifications
3.3.4
DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
≤
T
A
≤
85
°
C, or 3.0V to 3.6V and -40
°
C
≤
T
A
≤
85
°
C, respectively. Typical parameters apply to 5V and 3.3V at 25
°
C and
are for design guidance only.
Table 3-8. 5V DC Analog Output Buffer Specifications
Symbol
V
OSOB
TCV
OSOB
V
CMOB
R
OUTOB
Description
Min
Typ
Max
Units
mV
Notes
Input Offset Voltage (Absolute Value)
–
3
12
Average Input Offset Voltage Drift
–
+6
–
μ
V/°C
V
Common-Mode Input Voltage Range
0.5
–
Vdd - 1.0
Output Resistance
Power = Low
Power = High
High Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
Power = High
–
–
1
1
–
–
V
OHIGHOB
0.5 x Vdd
+ 1.3
0.5 x Vdd
+ 1.3
–
–
–
–
V
V
V
OLOWOB
Low Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
Power = High
–
–
–
–
0.5 x Vdd
- 1.3
0.5 x Vdd
- 1.3
V
V
I
SOB
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
Supply Voltage Rejection Ratio
–
–
60
1.1
2.6
–
5.1
8.8
–
mA
mA
dB
PSRR
OB
Table 3-9. 3.3V DC Analog Output Buffer Specifications
Symbol
V
OSOB
TCV
OSOB
V
CMOB
R
OUTOB
Description
Min
Typ
Max
Units
mV
Notes
Input Offset Voltage (Absolute Value)
–
3
12
Average Input Offset Voltage Drift
–
+6
–
μ
V/°C
V
Common-Mode Input Voltage Range
0.5
-
Vdd - 1.0
Output Resistance
Power = Low
Power = High
High Output Voltage Swing (Load = 1k ohms to Vdd/2)
Power = Low
Power = High
–
–
1
1
–
–
V
OHIGHOB
0.5 x Vdd
+ 1.0
0.5 x Vdd
+ 1.0
–
–
–
–
V
V
V
OLOWOB
Low Output Voltage Swing (Load = 1k ohms to Vdd/2)
Power = Low
Power = High
–
–
–
–
0.5 x Vdd
- 1.0
0.5 x Vdd
- 1.0
V
V
I
SOB
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
Supply Voltage Rejection Ratio
–
60
0.8
2.0
–
2.0
4.3
–
mA
mA
dB
PSRR
OB
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