- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379097 > CY8C22213-24SIT (CYPRESS SEMICONDUCTOR CORP) PSoC Mixed Signal Array PDF資料下載
參數(shù)資料
| 型號(hào)： | CY8C22213-24SIT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | PSoC Mixed Signal Array |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PDSO20 |
| 封裝： | 0.300 INCH, MO-119, SOIC-20 |
| 文件頁(yè)數(shù)： | 269/304頁(yè) |
| 文件大?。?/td> | 2956K |
| 代理商： | CY8C22213-24SIT |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)當(dāng)前第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)第273頁(yè)第274頁(yè)第275頁(yè)第276頁(yè)第277頁(yè)第278頁(yè)第279頁(yè)第280頁(yè)第281頁(yè)第282頁(yè)第283頁(yè)第284頁(yè)第285頁(yè)第286頁(yè)第287頁(yè)第288頁(yè)第289頁(yè)第290頁(yè)第291頁(yè)第292頁(yè)第293頁(yè)第294頁(yè)第295頁(yè)第296頁(yè)第297頁(yè)第298頁(yè)第299頁(yè)第300頁(yè)第301頁(yè)第302頁(yè)第303頁(yè)第304頁(yè)
December 22, 2003
Document No. 38-12009 Rev. *D
269
CY8C22xxx Preliminary Data Sheet
26. I2C
Bit 0: Byte Complete.
The I2C hardware operates on a
byte basis. In Transmit mode, this bit is set and an interrupt
is generated at the end of nine bits (the transmitted byte +
the received ACK). In Receive mode, the bit is set after the
eight bits of data have been received. When this bit is set,
an interrupt is generated at these data sampling points,
which are associated with the SCL input clock rising (see
details in the Timing section). If the host responds with a
write back to this register before the subsequent falling edge
of SCL (which is approximately one-half bit time), the trans-
fer will continue without interruption. However, if the host is
unable to respond within that time, the hardware will hold
the SCL line low, stalling the I2C bus. In both Master and
Slave mode, a subsequent write to the I2C_SCR register
will release the stall.
For additional information, reference the
I2C_SCR register
on page 126
.
26.3.3
I2C_DR Register
This register is the I2C data register and provides read/write
access to the shift register. It is not buffered and therefore,
writes and valid data reads may only occur at specific points
in the transfer. These cases are outlined as follows.
I
Master or Slave Receiver
Data in the I2C_DR register
is only valid for reading, when the Byte Complete status
bit is set. Data bytes must be read from the register
before writing to the I2C_SCR register, which continues
the transfer.
I
Master Start or Restart
Address bytes must be written
in I2C_DR before the Start or Restart bit is set in the
I2C_MSCR register, which causes the Start or Restart to
be generated and the address shifted out.
I
Master or Slave Transmitter
Data bytes must be writ-
ten to the I2C_DR register before the transmit bit is set in
the I2C_SCR register, which causes the transfer to con-
tinue.
For additional information, reference the
I2C_DR register on
page 127
.
26.3.4
I2C_MSCR Register
This register is the I2C master status and control register.
Bits 7 to 4: Reserved.
Bit 3: Bus Busy.
This read only bit is set to ‘1’ by any Start
condition and reset to ‘0’ by a Stop condition. It may be
polled by firmware to determine when a bus transfer may be
initiated.
Bit 2: Master Mode.
This bit indicates that the device is
operating as a Master. It is set in the detection of this block’s
Start condition and reset in the detection of the subsequent
Stop condition.
Bit 1: Restart Gen.
This bit is only used at the end of a
Master transfer (as noted in Other Cases 1 and 2 above of
the Start Gen bit). If an address is loaded into the data regis-
ter and this bit is set prior to NACKing (Master receiver) or
resetting the transmit bit (Master transmitter), or after a Mas-
ter transmitter is NACKed by the Slave, a Restart condition
will be generated, followed by the transmission of the
address byte.
Bit 0: Start Gen.
Before setting this bit, firmware must write
the address byte to send into the I2C_DR register. When
this bit is set, the Start condition is generated, followed
immediately by the transmission of the address byte. (No
control in the I2C_SCR register is needed for the Master to
initiate a transmission; the direction is inherently “transmit”.)
The bit is automatically reset to ‘0’ after the Start has been
generated.
There are three possible outcomes as a result of setting the
Start Gen bit:
1.
The bus is free and the Start condition is generated suc-
cessfully. A Byte Complete interrupt will be generated
after the Start and the address byte has been transmit-
ted. If the address was ACKed by the receiver, the firm-
ware may then proceed to send data bytes.
2.
The Start command is too late. Another Master in a
Multi-Master environment has generated a valid Start
and the bus is busy. The resulting behavior depends
upon whether Slave mode is enabled.
Slave mode is enabled: A Start and address byte inter-
rupt will be generated. When reading the I2C_MSCR,
the Master will see the Start Gen bit still set and the
I2C_SCR will have the Address bit set, indicating that
the block has been addressed as a Slave.
Table 26-6. I2C_MSCR Master Status and Control
Register
Bit
0
Access
R/W
Description
Mode
Master
Only
Start Gen
1 = Generate a Start condition and send a
byte (address) to the I2C bus.
This bit is cleared by hardware when the
Start generation is complete.
Restart Gen
1 = Generate a Restart condition.
This bit is cleared by hardware when the
Start generation is complete.
1
R/W
Master
Only
2
RO
Master Mode
This bit is set to ‘1’ when a start condition,
generated by this block, is detected and
reset to ‘0’ when a stop condition is
detected.
Bus Busy
This bit is set to ‘1’ when any Start condition
is detected, and reset to ‘0’ when a Stop
condition is detected.
Master
Only
3
RO
Master
Only
Table 26-6. I2C_MSCR Master Status and Control
Register
(continued)
Bit
Access
Description
Mode
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY8C24794-SPAX | PSoCTM Mixed-Signal Array |
| CY8C24794-SPE | PSoCTM Mixed-Signal Array |
| CY8C24794-SPI | Explosion-Proof Limit Switches Series CX: Short Housing: Top Plunger; 1NC 1NO SPDT Snap Action; Number of internal basic switches BZ: 1; 0.75 in - 14NPT conduit |
| CY8C24794-SPLFX | Environmentally sealed limit switch with Leadwire termination, Rotary Roller Lever actuation, Double Pole Double Throw (DPDT) Circuitry, 5 A (Resistive) ampere rating at 28 Vdc, Military Part Number MS21320-1 |
| CY8C24794-SPPVX | Environmentally sealed limit switch with Leadwire termination, Rotary Roller Lever actuation, Double Pole Double Throw (DPDT) Circuitry, 5 A (Resistive) ampere rating at 28 Vdc, Military Part Number MS21320-2 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY8C22345 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoC Programmable System-on-Chip |
| CY8C22345-12PVXE | 功能描述:可編程片上系統(tǒng) - PSoC M8C 8bit Flash 16KB RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:67 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT |
| CY8C22345-12PVXET | 功能描述:可編程片上系統(tǒng) - PSoC M8C 8bit Flash 16KB RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:67 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT |
| CY8C22345-24PVXA | 功能描述:可編程片上系統(tǒng) - PSoC 24 I/O 16K FLASH 1K SRAM RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:67 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT |
| CY8C22345-24PVXAT | 功能描述:可編程片上系統(tǒng) - PSoC 24 I/O 16K FLASH 1K SRAM RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:67 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。