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| 型號(hào)： | CY8C22213-24SIT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | PSoC Mixed Signal Array |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PDSO20 |
| 封裝： | 0.300 INCH, MO-119, SOIC-20 |
| 文件頁(yè)數(shù)： | 199/304頁(yè) |
| 文件大?。?/td> | 2956K |
| 代理商： | CY8C22213-24SIT |
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December 22, 2003
Document No. 38-12009 Rev. *D
199
CY8C22xxx Preliminary Data Sheet
17. Digital Blocks
17.2.1.2
Counter Register Definitions
DR1
Period
Write Only Register.
Data in this register sets the period of the count. The actual number of clocks counted is Period + 1.
In the default one-half cycle terminal count mode, a period value of 00h results in the primary output to be the inversion of
the input clock. In the optional full cycle terminal count mode, a period of 00h gives a constant logic high on the primary out-
put.
When disabled, a write to this register also transfers the period value directly into DR0.
When enabled, if the block frequency is 24 MHz or below, this register may be written to at any time, but the period will only
be reloaded into DR0 in the clock following a terminal count. If the block frequency is 48 MHz, the terminal count or compare
interrupt should be used to synchronize the new Period register write; otherwise, the counter could be incorrectly loaded.
Read Write Register (see Exception below).
DR2 has multiple functions in a Timer configuration. It is typically used as a Capture register, but it also functions as a Com-
pare register.
When enabled and a capture event occurs, the current count in DR0 is synchronously transferred into DR2.
When enabled, the compare output is computed using the Compare Type (set in the Function register mode bits) between
DR0 and DR2. The result of the Compare is output to the Auxiliary output.
When disabled, a read of DR0 will transfer the contents of DR0 into DR2 for the addressed block only.
Exception
: When enabled, DR2 is not writeable.
DR2
Capture/
Compare
Bank 0:
There are three 8-bit data registers and a 2-bit control register.
Table 17-7
explains the meaning of these registers in the context of the Counter
operation. Note that the descriptions of the registers are dependant on the enable/disable state of the block. This behavior is only related to the
enable bit in the Control register, not the data input that provides the counter gate (unless otherwise noted).
Bank 1:
The mode bits in the Function register are block type specific. Other bit fields in this register, as well as the definitions of the Input and Output reg-
isters are common to all functions. These mode bits are independent in the Counter block and control the Interrupt Type and the Compare Type
(same as the Timer function).
Table 17-7. Counter Data Register Descriptions
Name
Function
Count Value
Description
DR0
Not Directly Readable or Writeable.
During normal operation, DR0 stores the current count of a synchronous down counter.
When disabled, a write to the DR1 Period register is also simultaneously loaded into DR0 from the data bus.
When disabled or the data input (counter gate) is low, a read of DR0 returns 00h to the data bus and transfers the contents
of DR0 to DR2. This register should not be read when the counter is enabled and counting.
Write Only Register.
Data in this register sets the period of the count. The actual number of clocks counted is Period + 1.
In the default one-half cycle terminal count mode, a period value of 00h will result in the auxiliary output to be the inversion
of the input clock. In the optional full cycle terminal count mode, a period of 00h gives a constant logic high on the auxiliary
output.
When disabled, a write to this register also transfers the period value directly into DR0.
When enabled, if the block frequency is 24 MHz or below, this register may be written to at any time, but the period will only
be reloaded into DR0 in the clock following a terminal count. If the block frequency is 48 MHz, the terminal count or compare
interrupt should be used to synchronize the new Period register write; otherwise, the counter could be incorrectly loaded.
Read Write Register.
DR2 functions as a Compare register.
When enabled, the compare output is computed using the Compare Type (set in the Function register mode bits) between
DR0 and DR2. The result of the compare is output to the primary output.
When disabled or the data input (counter gate) is low, a read of DR0 will transfer the contents of DR0 into DR2.
DR2 may be written to when the function is enabled or disabled.
DR1
Period
DR2
Compare
Table 17-6. Timer Data Register Descriptions
(continued)
Name
Function
Description
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| CY8C24794-SPAX | PSoCTM Mixed-Signal Array |
| CY8C24794-SPE | PSoCTM Mixed-Signal Array |
| CY8C24794-SPI | Explosion-Proof Limit Switches Series CX: Short Housing: Top Plunger; 1NC 1NO SPDT Snap Action; Number of internal basic switches BZ: 1; 0.75 in - 14NPT conduit |
| CY8C24794-SPLFX | Environmentally sealed limit switch with Leadwire termination, Rotary Roller Lever actuation, Double Pole Double Throw (DPDT) Circuitry, 5 A (Resistive) ampere rating at 28 Vdc, Military Part Number MS21320-1 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CY8C22345 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoC Programmable System-on-Chip |
| CY8C22345-12PVXE | 功能描述:可編程片上系統(tǒng) - PSoC M8C 8bit Flash 16KB RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:67 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT |
| CY8C22345-12PVXET | 功能描述:可編程片上系統(tǒng) - PSoC M8C 8bit Flash 16KB RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:67 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT |
| CY8C22345-24PVXA | 功能描述:可編程片上系統(tǒng) - PSoC 24 I/O 16K FLASH 1K SRAM RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:67 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT |
| CY8C22345-24PVXAT | 功能描述:可編程片上系統(tǒng) - PSoC 24 I/O 16K FLASH 1K SRAM RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:67 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT |
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