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參數(shù)資料
| 型號(hào)： | CY8C22113 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | PSoC Mixed Signal Array |
| 中文描述： | PSoC混合信號(hào)陣列 |
| 文件頁(yè)數(shù)： | 56/304頁(yè) |
| 文件大小： | 2956K |
| 代理商： | CY8C22113 |
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6. General Purpose IO (GPIO)
CY8C22xxx Preliminary Data Sheet
56
Document No. 38-12009 Rev. *D
December 22, 2003
PRTxGS register. Also, the drive mode for the GPIO must
be set to the digital Hi-Z state. (Refer to
“PRTxDMx Regis-
ters” on page 58
for more information.) To configure a GPIO
as a global output, the port global select bit must again be
set. But in this case, the drive state must be set to any of the
non-Hi-Z states.
6.1.3
Analog IO
Analog signals can pass between the chip core and chip
pins through the block’s AOUT pin. This provides a resistive
path (~300 ohms) directly through the block. For analog
modes, the GPIO block is typically configured into a High
Impedance Analog Drive mode (Hi-Z).
6.1.4
GPIO Block Interrupts
Each GPIO block can be individually configured for interrupt
capability. Blocks are configured by pin interrupt enables
and also selection of the interrupt state. Blocks can be set to
interrupt when the pin is high, low, or when it changes from
the last time it was read. The block provides an open-drain
interrupt output (INTO) that is connected to other GPIO
blocks in a wire-OR fashion.
All pin interrupts that are wire-OR’ed together are tied to the
same system GPIO interrupt. Therefore, if interrupts are
enabled on multiple pins, the user’s interrupt service routine
must use some user designed mechanism, to determine
which pin was the source of the interrupt.
Using a GPIO interrupt requires the following steps:
1.
Set interrupt mode in the GPIO pin block.
2.
Enable the bit interrupt in the GPIO block.
3.
Set mask bit for the (global) GPIO interrupt.
4.
Assert the overall Global Interrupt Enable.
These last two steps are common to all interrupts and are
described in
“Interrupt Controller” on page 51
.
The first two steps, bit interrupt enable and interrupt mode,
are set at the GPIO block level (i.e., at each port pin), by
way of the block’s configuration registers.
At the GPIO block level, asserting the INTO line depends
only on the bit interrupt enable and the state of the pin rela-
tive to the chosen interrupt mode. At the chip level, due to
their wire-OR nature, the GPIO interrupts are neither true
edge-sensitive interrupts nor true level-sensitive interrupts.
They could be considered edge-sensitive for asserting, but
level-sensitive for release of the wire-OR interrupt line.
If no GPIO interrupts are asserting, a GPIO interrupt will
occur whenever a GPIO pin Interrupt Enable is set and the
GPIO pin transitions (if not already transitioned) appropri-
ately high or low (to match the interrupt mode configuration).
Once this happens, the INTO line will pull low to assert the
GPIO interrupt. (This assumes the other system-level
enables are on, such as setting the global GPIO interrupt
enable and the Global Interrupt Enable.) Note that setting
the pin Interrupt Enable may immediately assert INTO, if the
Interrupt Mode conditions are already being met at the pin.
Once INTO pulls low, it will continue to hold INTO low until
one of these conditions changes: a.) the pin Interrupt Enable
is cleared; b.) the voltage at PIN transitions to the opposite
state; c.) in interrupt-on-change mode, the GPIO data regis-
ter is read, thus setting the local interrupt level to the oppo-
site state; or d.) the interrupt mode is changed so that the
current pin state does not create an interrupt. Once one of
these conditions is met, the INTO releases. At this point,
another GPIO pin (or this pin again) could assert its INTO
pin, pulling the common line low to assert a new interrupt.
Note the following behavior from this level-release feature. If
one pin is asserting INTO and then a second pin asserts its
INTO, when the first pin releases its INTO, the second pin is
already driving INTO and thus no change will be seen, i.e.,
no new interrupt would be asserted on the GPIO interrupt.
Care must be taken, using polling and/or the states of the
GPIO pin and global Interrupt Enables, to catch all interrupts
among a set of wire-OR GPIO blocks.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY8C22113-24PI | PSoC Mixed Signal Array |
| CY8C22113-24SI | PSoC Mixed Signal Array |
| CY8C22213 | PSoC Mixed Signal Array |
| CY8C22213-24LFI | PSoC Mixed Signal Array |
| CY8C22213-24PI | PSoC Mixed Signal Array |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY8C22113_04 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoC⑩ Mixed Signal Array |
| CY8C22113-24PI | 功能描述:IC MCU 2K FLASH 256B 8-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:PSOC®1 CY8C22xxx 標(biāo)準(zhǔn)包裝:60 系列:BlueStreak ; LH7 核心處理器:ARM7 芯體尺寸:32-位 速度:84MHz 連通性:EBI/EMI，SPI，SSI，SSP，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，DMA，LCD，POR，PWM，WDT 輸入/輸出數(shù):76 程序存儲(chǔ)器容量:- 程序存儲(chǔ)器類型:ROMless EEPROM 大小:- RAM 容量:32K x 8 電壓 - 電源 (Vcc/Vdd):1.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤 |
| CY8C22113-24SI | 功能描述:IC MCU 2K FLASH 256B 8-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:PSOC®1 CY8C22xxx 標(biāo)準(zhǔn)包裝:60 系列:BlueStreak ; LH7 核心處理器:ARM7 芯體尺寸:32-位 速度:84MHz 連通性:EBI/EMI，SPI，SSI，SSP，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，DMA，LCD，POR，PWM，WDT 輸入/輸出數(shù):76 程序存儲(chǔ)器容量:- 程序存儲(chǔ)器類型:ROMless EEPROM 大小:- RAM 容量:32K x 8 電壓 - 電源 (Vcc/Vdd):1.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤 |
| CY8C22113-24SIT | 功能描述:IC MCU 2K FLASH 256B 8-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:PSOC®1 CY8C22xxx 標(biāo)準(zhǔn)包裝:60 系列:BlueStreak ; LH7 核心處理器:ARM7 芯體尺寸:32-位 速度:84MHz 連通性:EBI/EMI，SPI，SSI，SSP，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，DMA，LCD，POR，PWM，WDT 輸入/輸出數(shù):76 程序存儲(chǔ)器容量:- 程序存儲(chǔ)器類型:ROMless EEPROM 大小:- RAM 容量:32K x 8 電壓 - 電源 (Vcc/Vdd):1.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤 |
| CY8C22213 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoC⑩ Mixed Signal Array |
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