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| 型號(hào)： | CY8C21634-24AX |
| 廠(chǎng)商： | Cypress Semiconductor Corp. |
| 英文描述： | PSoC Mixed-Signal Array |
| 中文描述： | PSoC混合信號(hào)陣列 |
| 文件頁(yè)數(shù)： | 11/35頁(yè) |
| 文件大?。?/td> | 376K |
| 代理商： | CY8C21634-24AX |
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April 20, 2005
Document No. 38-12025 Rev. *G
11
CY8C21x34 Final Data Sheet
1. Pin Information
1.1.4
32-Pin Part Pinout
Table 1-4. 32-Pin Part Pinout (MLF*)
Pin
No.
Type
Name
Description
CY8C21434 32-Pin PSoC Device
P
Digital
IO
Analog
I, M
1
P0[1]
Analog column mux input, integrating
input.
2
3
4
5
6
6
IO
IO
IO
IO
IO
M
M
M
M
M
P2[7]
P2[5]
P2[3]
P2[1]
P3[3]
SMP
In CY8C21434 part.
Switch Mode Pump (SMP) connection to
required external components in
CY8C21634 part.
In CY8C21434 part.
Ground connection in CY8C21634 part.
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
Power
7
7
8
9
10
11
12
13
14
15
16
17
IO
M
P3[1]
Vss
P1[7]
P1[5]
P1[3]
P1[1]
Vss
P1[0]
P1[2]
P1[4]
P1[6]
XRES
Power
IO
IO
IO
IO
M
M
M
M
I2C Serial Clock (SCL), ISSP-SCLK.
Ground connection.
I2C Serial Data (SDA), ISSP-SDATA.
Power
IO
IO
IO
IO
M
M
M
M
Optional External Clock Input (EXTCLK).
Input
Active high external reset with internal
pull down.
CY8C21634 32-Pin PSoC Device
P
18
19
20
21
22
23
24
25
26
27
28
29
30
31
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
M
M
M
M
M
M
I, M
I, M
I, M
I, M
P3[0]
P3[2]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
P0[7]
P0[5]
P0[3]
Analog column mux input.
Analog column mux input.
Analog column mux input.
Analog column mux input.
Supply voltage.
Analog column mux input.
Analog column mux input.
Analog column mux input, integrating
input.
Ground connection.
Power
IO
IO
IO
I, M
I, M
I, M
32
Power
Vss
LEGEND
A = Analog, I = Input, O = Output, and M = Analog Mux Input.
* The MLF package has a center pad that must be connected to ground
(Vss).
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
M, P3[3]
M, P3[1]
M, I2C SCL, P1[7]
MLF
(Top View)
9
1
1
1
1
1
1
1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
3
3
3
2
2
2
2
2
V
P
V
P
P
P
P0[0], A, I, M
P2[6], M
P2[4], M
P2[2], M
P2[0], M
P3[2], M
P3[0], M
XRES
M
M
M
V
M
M
M
M
P
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
SMP
Vss
MLF
(Top View)
9
1
1
1
1
1
1
1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
3
3
3
2
2
2
2
2
V
P
V
P
P
P
M, I2C SCL, P1[7]
P0[0], A, I, M
P2[6], M
P2[4], M
P2[2], M
P2[0], M
P3[2], M
P3[0], M
XRES
M
M
M
V
M
M
M
M
P
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY8C21534 | PSoC Mixed-Signal Array |
| CY8C21234-24LFX | PQ I HIP6W DUET |
| CY8C21434-24LFX | PSoC Mixed-Signal Array |
| CY8C21534-24LFX | PSoC Mixed-Signal Array |
| CY8C21234-24PVX | PSoC Mixed-Signal Array |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY8C21634-24C | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:PSoC Mixed-Signal Array |
| CY8C21634-24E | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:PSoC Mixed-Signal Array |
| CY8C21634-24I | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:PSoC Mixed-Signal Array |
| CY8C21634-24LFX | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:PSoC Mixed-Signal Array |
| CY8C21634-24LFXI | 功能描述:可編程片上系統(tǒng) - PSoC IC MCU 8K FLASH 512B SRAM RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:67 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT |
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