參數(shù)資料
型號： CY8C21223
廠商： Cypress Semiconductor Corp.
英文描述： PSoC Mixed-Signal Array(PSoC混合信號陣列)
中文描述： PSoC混合信號陣列（的PSoC混合信號陣列）
文件頁數(shù)： 21/33頁
文件大?。?/td> 325K
代理商： CY8C21223
February 25, 2005
Document No. 38-12022 Rev. *G
21
CY8C21x23 Final Data Sheet
3. Electrical Specifications
3.4
AC Electrical Characteristics
3.4.1
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
≤
T
A
≤
85
°
C, 3.0V to 3.6V and -40
°
C
≤
T
A
≤
85
°
C, or 2.4V to 3.0V and -40
°
C
≤
T
A
≤
85
°
C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25
°
C and are for design guidance only..
Table 3-13. 5V and 3.3V AC Chip-Level Specifications
Symbol
F
IMO24
Description
Min
Typ
Max
Units
MHz
Notes
Internal Main Oscillator Frequency for 24 MHz
23.4
24
24.6
a,b,c
Trimmed for 5V or 3.3V operation using
factory trim values. See Figure 3-1b on
page 14
. SLIMO mode = 0.
Trimmed for 3.3V operation using factory
trim values. See Figure 3-1b on
page 14
.
SLIMO mode = 1.
24 MHz only for SLIMO mode = 0.
F
IMO6
Internal Main Oscillator Frequency for 6 MHz
5.75
6
6.35
a,b,c
MHz
F
CPU1
F
CPU2
F
BLK5
CPU Frequency (5V Nominal)
0.93
24
24.6
a,b
12.3
b,
c
49.2
a,b,d
a. 4.75V < Vdd < 5.25V.
b. Accuracy derived fromInternal Main Oscillator with appropriate trimfor Vdd range.
c. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimmng for operation at 3.3V.
d. See the individual user module data sheets for information on maximumfrequencies for user modules.
MHz
CPU Frequency (3.3V Nominal)
0.93
12
MHz
Digital PSoC Block Frequency
0
(5V Nominal)
0
48
MHz
Refer to the AC Digital Block Specifica-
tions below.
F
BLK33
F
32K1
Jitter32k
Jitter32k
T
XRST
DC24M
Step24M
Fout48M
Jitter24M1
F
MAX
T
RAMP
Digital PSoC Block Frequency (3.3V Nominal)
Internal Low Speed Oscillator Frequency
0
15
24
32
24.6
b,d
64
MHz
kHz
32 kHz RMS Period Jitter
32 kHz Peak-to-Peak Period Jitter
External Reset Pulse Width
24 MHz Duty Cycle
24 MHz Trim Step Size
48 MHz Output Frequency
24 MHz Peak-to-Peak Period Jitter (IMO)
Maximum frequency of signal on row input or row output.
Supply Ramp Time
–
–
10
40
–
46.8
–
–
0
100
1400
–
50
50
48.0
300
–
–
200
–
–
60
–
49.2
a,c
ns
ns
μ
s
%
kHz
MHz
ps
MHz
μ
s
Trimmed. Utilizing factory trim values.
12.3
–
Table 3-14. 2.7V AC Chip-Level Specifications
Symbol
F
IMO12
Description
Min
Typ
Max
Units
MHz
Notes
Internal Main Oscillator Frequency for 12 MHz
11.5
12
0
12.7
a,b,c
Trimmed for 2.7V operation using factory
trim values. See Figure 3-1b on
page 14
.
SLIMO mode = 1.
Trimmed for 2.7V operation using factory
trim values. See Figure 3-1b on
page 14
.
SLIMO mode = 1.
24 MHz only for SLIMO mode = 0.
F
IMO6
Internal Main Oscillator Frequency for 6 MHz
5.5
6
6.35
a,b,c
MHz
F
CPU1
F
BLK27
CPU Frequency (2.7V Nominal)
0.093
3
3.15
a,b
12.5
a,b,c
a. 2.4V < Vdd < 3.0V.
b. Accuracy derived fromInternal Main Oscillator with appropriate trimfor Vdd range.
c. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on maximumfrequency for user modules.
MHz
Digital PSoC Block Frequency (2.7V Nominal)
0
12
MHz
Refer to the AC Digital Block Specifica-
tions below.
F
32K1
Jitter32k
Jitter32k
T
XRST
F
MAX
T
RAMP
Internal Low Speed Oscillator Frequency
8
32
96
kHz
32 kHz RMS Period Jitter
32 kHz Peak-to-Peak Period Jitter
External Reset Pulse Width
Maximum frequency of signal on row input or row output.
Supply Ramp Time
–
–
10
–
0
150
1400
–
–
–
200
–
–
12.3
–
ns
ns
μ
s
MHz
μ
s
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