參數(shù)資料
型號(hào)： CY8C21223
廠商： Cypress Semiconductor Corp.
英文描述： PSoC Mixed-Signal Array(PSoC混合信號(hào)陣列)
中文描述： PSoC混合信號(hào)陣列（的PSoC混合信號(hào)陣列）
文件頁(yè)數(shù)： 2/33頁(yè)
文件大?。?/td> 325K
代理商： CY8C21223
February 25, 2005
Document No. 38-12022 Rev. *G
2
CY8C21x23 Final Data Sheet
PSoC Overview
CPU core, called the M8C, is a powerful processor with speeds
up to 24 MHz. The M8C is a four MIPS 8-bit Harvard architec-
ture microprocessor.
System Resources provide additional capability, such as digital
clocks to increase the flexibility of the PSoC mixed-signal
arrays, I2C functionality for implementing an I2C master, slave,
MultiMaster, an internal voltage reference that provides an
absolute value of 1.3V to a number of PSoC subsystems, a
switch mode pump (SMP) that generates normal operating volt-
ages off a single battery cell, and various system resets sup-
ported by the M8C.
The Digital System is composed of an array of digital PSoC
blocks, which can be configured into any number of digital
peripherals. The digital blocks can be connected to the GPIO
through a series of global busses that can route any signal to
any pin. Freeing designs from the constraints of a fixed periph-
eral controller.
The Analog System is composed of four analog PSoC blocks,
supporting comparators and analog-to-digital conversion up to
8 bits in precision.
The Digital System
The Digital System is composed of 4 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references. Digital peripheral configura-
tions include those listed below.
■
PWMs (8 to 32 bit)
■
PWMs with Dead band (8 to 32 bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
UART 8 bit with selectable parity (up to 4)
■
SPI master and slave
■
I2C slave, master, multi-master (1 available as a System
Resource)
■
Cyclical Redundancy Checker/Generator (8 to 32 bit)
■
IrDA (up to 4)
■
Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global busses that can route any signal to any pin. The
busses also allow for signal multiplexing and for performing
logic operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the opti-
mum choice of system resources for your application. Family
resources are shown in the table titled
“PSoC Device Charac-
teristics” on page 3
.
Digital System Block Diagram
The Analog System
The Analog System is composed of 4 configurable blocks to
allow creation of complex analog signal flows. Analog peripher-
als are very flexible and can be customized to support specific
application requirements. Some of the more common PSoC
analog functions (most available as user modules) are listed
below.
■
Analog-to-digital converters (single or dual, with 8-bit resolu-
tion)
■
Pin-to-pin comparators (1)
■
Single-ended comparators (up to 2) with absolute (1.3V) ref-
erence or 8-bit DAC reference
■
1.3V reference (as a System Resource)
In most PSoC devices, analog blocks are provided in columns
of three, which includes one CT (Continuous Time) and two SC
(Switched Capacitor) blocks. The CY8C21x23 devices provide
limited functionality Type “E” analog blocks. Each column con-
tains one CT block and one SC block.
The number of blocks is on the device family which is detailed
in the table titled
“PSoC Device Characteristics” on page 3
.
DIGITAL SYSTEM
To System Bus
Digital Clocks
From Core
Digital PSoC Block Array
To Analog
System
8
R
C
R
C
8
8
8
Row 0
DBB00
DBB01
DCB02
DCB03
4
4
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
Port 1
Port 0
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