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參數(shù)資料
| 型號(hào)： | CY7C9235A |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SMPTE-259M/DVB-ASI Scrambler/Controller(SMPTE-259M/DVB-ASI擾頻器/控制器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大?。?/td> | 95K |
| 代理商： | CY7C9235A |
CY7C9235A
Document #: 38-02082 Rev. **
Page 3 of 8
SC/D_EN
Input
Special Character/Data Select Enable
. This input is only valid when DVB_EN is active (LOW). If
SC/D_EN is HIGH and a HIGH input is present on PD
0
, Q
0
will also be high on a following clock
cycle, forcing the CY7B9234 serializer to generate an 8B/10B control character as selected by the
character present on the PD
8–1
inputs. If SC/D_EN is LOW, the level present on PD
0
is ignored and
Q
0
is forced to a LOW (data only) state.
Parallel Data 9 or Send Violation Symbol
. This is the MSB of the input data field. It is latched in
the input register at the rising edge of CKW. When DVB_EN is active (LOW) and SVS_EN is HIGH,
this latched input is routed to the output register bit Q
9
(SVS). When DVB_EN is active (LOW) and
SVS_EN is LOW, output register bit Q
9
(SVS) is forced to a LOW (zero) level. When DVB_EN is
inactive (HIGH), this latched input is routed to the scrambler and NRZI encoder.
Parallel Data 8 through 1
. The signals present at the PD
8–1
inputs are latched in the input register
at the rising edge of CKW. When DVB_EN is HIGH, these signals are the middle eight bits of the
SMPTE 10-bit data field, and are then routed to the scrambler and NRZI encoder. When DVB_EN
is active (LOW), these signals are full DVB-ASI data bus, and are then routed to the Q
8
1
outputs.
Parallel Data 0 or Special Code/Data Select
. This is the LSB of the input data field. It is latched in
the input register at the rising edge of CKW. When DVB_EN is active (LOW) and SC/D_EN is HIGH,
this input is routed to output register bit Q
0
(SVS). When DVB_EN is active (LOW) and SC/D_EN is
LOW, output register bit Q
0
(SC/D) is forced to a LOW (zero) level. When DVB_EN is inactive (HIGH),
this input data bit is routed through the input register and the scrambler and NRZI encoder.
Output Bit 9
. This is the MSB of the output register. It should be connected directly to the CY7B9234
serializer input signal SVS(Dj).
Output Bits 8 through 1
. These signals should be connected directly to the CY7B9234 serializer
input signals D
7
0
respectively.
Output Bit 0
. This is the LSB of the output register. It should be connected directly to the CY7B9234
serializer input signal SC/D(Da).
DVB Mode Enable
. This signal is sampled by the rising edge of the CKW clock. If DVB_EN is active
(LOW), the data present on the PD
0
9
, ENA, and ENN inputs are latched and routed to the Q
0
9
and
ENA_OUT outputs.
Clock Write
. This clock controls all synchronous operations of the CY7C9235A. It operates at the
character rate which is equivalent to one tenth the serialized bit-rate. This clock also connects directly
to the CKW input of the CY7B9234 serializer.
Enable Parallel Data Out
. This output attached directly to the CY7B9234 ENA input, and identifies
when valid data is available at the CY7C9235A outputs. If used only for SMPTE-259M data streams,
this output may be left open, with the ENA input to the CY7B9234 directly connected to V
SS
.
Output Enable
. When this signal is HIGH all outputs are driven to their normal logic levels. When
LOW, all outputs are placed in a High-Z state.
Power
.
Ground
.
PD
9
(SVS)
Input
PD
8–1
Input
PD
0
(SC/D)
Input
Q
9
(SVS)
Output
Q
8–1
Output
Q
0
(SC/D)
Output
DVB_EN
Input
CKW
Input
ENA_OUT
Output
OE
Input
V
CC
V
SS
Pin Descriptions
CY7C9235A SMPTE-259M Encoder (continued)
Name
I/O
Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C9235A-270JC | 制造商:Cypress Semiconductor 功能描述:SMPTE-259M/DVB-ASI Scrambler/Controller 44-Pin PLCC 制造商:Rochester Electronics LLC 功能描述: |
| CY7C9235A-270JXC | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 SMPTE Encoder RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| CY7C924ADX-AC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C924ADX-ADI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C924ADX-AI | 制造商:Cypress Semiconductor 功能描述:Framer 5V 100-Pin TQFP |
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