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參數(shù)資料
| 型號： | CY7C9235A |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SMPTE-259M/DVB-ASI Scrambler/Controller(SMPTE-259M/DVB-ASI擾頻器/控制器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 95K |
| 代理商： | CY7C9235A |
CY7C9235A
Document #: 38-02082 Rev. **
Page 2 of 8
Pin Configuration
1
44
43
42
41
40
2
3
4
5
6
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
7
8
9
10
11
12
13
14
15
16
17
BYPASS
V
SS
SVS_EN
OE
NC
V
SS
NC
PD
9
(SVS)
NC
NC
V
SS
V
SS
V
SS
CKW
ENA_OUT
Q
0
(SC/D)
ENN
ENA
SC/D_EN
DVB_EN
TRS_FILT
TRS_DET
Q
2
Q
3
Q
4
V
C
V
S
Q
5
Q
6
Q
7
Q
8
Q
9
(
Q
1
V
S
P
4
P
3
P
2
P
1
P
0
(
V
C
P
5
P
6
P
7
P
8
V
SS
PLCC
Top View
Pin Descriptions
CY7C9235A SMPTE-259M Encoder
Name
I/O
Description
ENA
Input
Enable Parallel Data
. If ENA is LOW at the rising edge of CKW, the data present on the PD
0
9
inputs
is latched, and routed to the Q
0–9
outputs. This pin is only interpreted when DVB_EN is active (LOW).
If the CY7C9235A is only used in SMPTE-259M mode this signal should be tied to V
SS
.
Enable Next Parallel Data
. If ENN is LOW at the rising edge of CKW, the data present on the PD
0–9
inputs at the next rising edge of TXCLK is latched, and routed to the Q
0–9
outputs. This pin is only
interpreted when DVB_EN is active (LOW). If the CY7C9235A is only used in SMPTE-259M mode
this signal should be tied to V
SS
.
Bypass SMPTE Encoding
. BYPASS is ignored if DVB_EN is active (LOW). If BYPASS is HIGH at
the rising edge of CKW (and DVB_EN is HIGH), the data latched into the input register is routed
around both the SMPTE scrambler and the NRZI encoder and presented to the output register. If
BYPASS is LOW at the rising edge of the CKW clock (and DVB_EN is HIGH), the data present in
the input register is routed through the SMPTE scrambler and NRZI encoder.
TRS Character Detected
. This output indicates when a character used in the TRS sequence is
detected in the input register. If the data contains any of the reserved characters of 000–003 or
3FC–3FF in 10-bit hex, the output will be LOW for one clock period. If the character in the input
register is any other pattern (or DVB_EN is LOW) this output will remain HIGH.
TRS Character Filter
. This signal controls an internal filter that converts the low-order two bits of all
TRS characters to same state as the upper eight bits. This allows a proper 30-bit TRS ID to be
generated when the CY7C9235A is operated with 8-bit or non-standard video streams. When this
signal is LOW, all characters from 000–003 are converted to 000, and all characters from 3FC–3FF
are converted to 3FF. When TRS_FILT is disabled (HIGH), all characters are passed to the scrambler
without modification. This signal has no effect when DVB_EN is active (LOW).
Send Violation Symbol Enable
. This input is only valid when DVB_EN is active (LOW). If SVS_EN
is HIGH and a HIGH input is present on PD
9
, Q
9
will also be high on a following clock cycle, forcing
the CY7B9234 serializer to generate an invalid 8B/10B character. If SVS_EN is LOW, the level
present on PD
9
is ignored and Q
9
is forced to a LOW state.
ENN
Input
BYPASS
Input
TRS_DET
Output
TRS_FILT
Input
SVS_EN
Input
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C9235A-270JC | 制造商:Cypress Semiconductor 功能描述:SMPTE-259M/DVB-ASI Scrambler/Controller 44-Pin PLCC 制造商:Rochester Electronics LLC 功能描述: |
| CY7C9235A-270JXC | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 SMPTE Encoder RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| CY7C924ADX-AC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C924ADX-ADI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C924ADX-AI | 制造商:Cypress Semiconductor 功能描述:Framer 5V 100-Pin TQFP |
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