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參數(shù)資料
| 型號： | CY7C68015A-56LFXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | EZ-USB FX2LP USB Microcontroller |
| 中文描述： | 8-BIT, EEPROM, 48 MHz, MICROCONTROLLER, QCC56 |
| 封裝： | 8 X 8 MM, LEAD FREE, MO-220, QFN-56 |
| 文件頁數(shù)： | 50/55頁 |
| 文件大?。?/td> | 1958K |
| 代理商： | CY7C68015A-56LFXC |
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CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Document #: 38-08032 Rev. *G
Page 50 of 55
9.16.4
Sequence Diagram of a Single and Burst Asynchronous Write
Figure 9-21
diagrams the timing relationship of the SLAVE
FIFO write in an asynchronous mode. The diagram shows a
single write followed by a burst write of 3 bytes and committing
the 4-byte-short packet using PKTEND.
·At t = 0 the FIFO address is applied, insuring that it meets the
set-up time of t
SFA
. If SLCS is used, it must also be asserted
(SLCS may be tied low in some applications).
·..At t = 1 SLWR is asserted. SLWR must meet the minimum
active pulse of t
WRpwl
and minimum de-active pulse width of
t
WRpwh
. If the SLCS is used, it must be in asserted with SLWR
or before SLWR is asserted.
·At t = 2, data must be present on the bus t
SFD
before the de-
asserting edge of SLWR.
·At t = 3, de-asserting SLWR will cause the data to be written
from the data bus to the FIFO and then increments the FIFO
pointer. The FIFO flag is also updated after t
XFLG
from the de-
asserting edge of SLWR.
The same sequence of events are shown for a burst write and
is indicated by the timing marks of T = 0 through 5. Note: In
the burst write mode, once SLWR is deasserted, the data is
written to the FIFO and then the FIFO pointer is incremented
to the next byte in the FIFO. The FIFO pointer is post incre-
mented.
In
Figure 9-21
once the four bytes are written to the FIFO and
SLWR is deasserted, the short 4-byte packet can be
committed to the host using the PKTEND. The external device
should be designed to not assert SLWR and the PKTEND
signal at the same time. It should be designed to assert the
PKTEND after SLWR is de-asserted and met the minimum de-
asserted pulse width. The FIFOADDR lines are to be held
constant during the PKTEND assertion.
PKTEND
SLWR
FLAGS
DATA
Figure 9-21. Slave FIFO Asynchronous Write Sequence and Timing Diagram
[19]
t
WRpwh
t
WRpwl
t
XFLG
N
t
SFD
N+1
t
XFLG
t
SFA
t
FAH
FIFOADR
SLCS
t
WRpwh
t
WRpwl
t
WRpwh
t
WRpwl
t
WRpwh
t
WRpwl
t
FAH
t
SFA
t
FDH
t
SFD
N+2
t
FDH
t
SFD
N+3
t
FDH
t
SFD
t
FDH
t
PEpwh
t
PEpwl
t=0
t=2
t =1
t=3
T=0
T=2
T=1
T=3
T=6
T=9
T=5
T=8
T=4
T=7
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C68015A-56LTXC | 功能描述:USB 接口集成電路 USB HS Controller RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| CY7C68015A-56LTXCKA | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C68015A-56PVXC | 功能描述:8位微控制器 -MCU EZ USB FX2LP LO PWR Extra GPIO COM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| CY7C68016A-56LFXC | 功能描述:8位微控制器 -MCU EZ USB FX2LP Battery Apps Extra GPIO COM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| CY7C68016A-56LFXCT | 功能描述:8位微控制器 -MCU EZ-USB FX2LP,Ex GPIO RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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