參數(shù)資料
型號： CY7C68014A-56PVXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： EZ-USB FX2LP USB Microcontroller
中文描述： 8-BIT, EEPROM, 48 MHz, MICROCONTROLLER, PDSO56
封裝： LEAD FREE, SSOP-56
文件頁數(shù)： 44/55頁
文件大?。?/td> 1958K
代理商： CY7C68014A-56PVXC
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Document #: 38-08032 Rev. *G
Page 44 of 55
that needs attention while using the PKTEND to commit a one
byte/word packet. There is an additional timing requirement
that need to be met when the FIFO is configured to operate in
auto mode and it is desired to send two packets back to back:
a full packet (full defined as the number of bytes in the FIFO
meeting the level set in AUTOINLEN register) committed
automatically followed by a short one byte/word packet
committed manually using the PKTEND pin. In this particular
scenario, user must make sure to assert PKTEND atleast one
clock cycle after the rising edge that caused the last byte/word
to be clocked into the previous auto committed packet. Figure
9-10 below shows this scenario. X is the value the
AUTOINLEN register is set to when the IN endpoint is
configured to be in auto mode.
The above figure shows a scenario where two packets are
being committed. The first packet gets comitted automatically
when the number of bytes in the FIFO reaches X (value set in
AUTOINLEN register) and the second one byte/word short
packet being committed manually using PKTEND. Note that
there is atleast one IFCLK cycle timing between the assertion
of PKTEND and clocking of the last byte of the previous packet
(causing the packet to be committed automatically). Failing to
adhere to this timing, will result in the FX2 failing to send the
one byte/word short packet.
9.11
Slave FIFO Asynchronous Packet End Strobe
IFCLK
SLWR
DATA
Figure 9-10. Slave FIFO Synchronous Write Sequence and Timing Diagram
t
IFCLK
>= t
SWR
>= t
WRH
X-2
PKTEND
X-3
t
FAH
t
SPE
t
PEH
FIFOADR
t
SFD
t
SFD
t
SFD
X-4
t
FDH
t
FDH
t
FDH
t
SFA
1
X
t
SFD
t
SFD
t
SFD
X-1
t
FDH
t
FDH
t
FDH
At least one IFCLK cycle
Table 9-14. Slave FIFO Asynchronous Packet End Strobe Parameters
[23]
Parameter
t
PEpwl
t
PWpwh
t
XFLG
Description
Min.
50
50
Max.
Unit
ns
ns
ns
PKTEND Pulse Width LOW
PKTEND Pulse Width HIGH
PKTEND to FLAGS Output Propagation Delay
115
FLAGS
t
XFLG
PKTEND
t
PEpwl
t
PEpwh
Figure 9-11. Slave FIFO Asynchronous Packet End Strobe Timing Diagram
[19]
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相關代理商/技術參數(shù)
參數(shù)描述
CY7C68014A-BAXC 制造商:Cypress Semiconductor 功能描述:MCU 8BIT CISC ROMLESS 3.3V 100TQFP - Trays
CY7C68015A-56LFXC 功能描述:8位微控制器 -MCU EZ USB FX2LP LO PWR Extra GPIO COM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
CY7C68015A-56LTXC 功能描述:USB 接口集成電路 USB HS Controller RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
CY7C68015A-56LTXCKA 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
CY7C68015A-56PVXC 功能描述:8位微控制器 -MCU EZ USB FX2LP LO PWR Extra GPIO COM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
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