參數(shù)資料
型號: CY7C68014A-56PVXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: EZ-USB FX2LP USB Microcontroller
中文描述: 8-BIT, EEPROM, 48 MHz, MICROCONTROLLER, PDSO56
封裝: LEAD FREE, SSOP-56
文件頁數(shù): 23/55頁
文件大?。?/td> 1958K
代理商: CY7C68014A-56PVXC
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Document #: 38-08032 Rev. *G
Page 23 of 55
54
44
29
22
PB4 or
FD[4]
I/O/Z
I
(PB4)
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB4
is a bidirectional I/O port pin.
FD[4]
is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB5
is a bidirectional I/O port pin.
FD[5]
is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB6
is a bidirectional I/O port pin.
FD[6]
is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB7
is a bidirectional I/O port pin.
FD[7]
is the bidirectional FIFO/GPIF data bus.
55
45
30
23
PB5 or
FD[5]
I/O/Z
I
(PB5)
56
46
31
24
PB6 or
FD[6]
I/O/Z
I
(PB6)
57
47
32
25
PB7 or
FD[7]
I/O/Z
I
(PB7)
PORT C
72
57
PC0 or
GPIFADR0
I/O/Z
I
(PC0)
Multiplexed pin whose function is selected by
PORTCCFG.0
PC0
is a bidirectional I/O port pin.
GPIFADR0
is a GPIF address output pin.
Multiplexed pin whose function is selected by
PORTCCFG.1
PC1
is a bidirectional I/O port pin.
GPIFADR1
is a GPIF address output pin.
Multiplexed pin whose function is selected by
PORTCCFG.2
PC2
is a bidirectional I/O port pin.
GPIFADR2
is a GPIF address output pin.
Multiplexed pin whose function is selected by
PORTCCFG.3
PC3
is a bidirectional I/O port pin.
GPIFADR3
is a GPIF address output pin.
Multiplexed pin whose function is selected by
PORTCCFG.4
PC4
is a bidirectional I/O port pin.
GPIFADR4
is a GPIF address output pin.
Multiplexed pin whose function is selected by
PORTCCFG.5
PC5
is a bidirectional I/O port pin.
GPIFADR5
is a GPIF address output pin.
Multiplexed pin whose function is selected by
PORTCCFG.6
PC6
is a bidirectional I/O port pin.
GPIFADR6
is a GPIF address output pin.
Multiplexed pin whose function is selected by
PORTCCFG.7
PC7
is a bidirectional I/O port pin.
GPIFADR7
is a GPIF address output pin.
73
58
PC1 or
GPIFADR1
I/O/Z
I
(PC1)
74
59
PC2 or
GPIFADR2
I/O/Z
I
(PC2)
75
60
PC3 or
GPIFADR3
I/O/Z
I
(PC3)
76
61
PC4 or
GPIFADR4
I/O/Z
I
(PC4)
77
62
PC5 or
GPIFADR5
I/O/Z
I
(PC5)
78
63
PC6 or
GPIFADR6
I/O/Z
I
(PC6)
79
64
PC7 or
GPIFADR7
I/O/Z
I
(PC7)
PORT D
102
80
52
45
PD0 or
FD[8]
I/O/Z
I
(PD0)
Multiplexed pin whose function is selected by the
IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
FD[8]
is the bidirectional FIFO/GPIF data bus.
Table 4-1. FX2LP Pin Descriptions
(continued)
[10]
128
TQFP
100
TQFP
56
SSOP
56
QFN
Name
Type
Default
Description
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CY7C68015A-56LTXCKA 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
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