參數(shù)資料
型號(hào): CY7C68014A-56PVXC
廠(chǎng)商: CYPRESS SEMICONDUCTOR CORP
元件分類(lèi): 微控制器/微處理器
英文描述: EZ-USB FX2LP USB Microcontroller
中文描述: 8-BIT, EEPROM, 48 MHz, MICROCONTROLLER, PDSO56
封裝: LEAD FREE, SSOP-56
文件頁(yè)數(shù): 22/55頁(yè)
文件大?。?/td> 1958K
代理商: CY7C68014A-56PVXC
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Document #: 38-08032 Rev. *G
Page 22 of 55
84
69
42
35
PA2 or
SLOE or
I/O/Z
I
(PA2)
Multiplexed pin whose function is selected by two bits:
IFCONFIG[1:0].
PA2
is a bidirectional IO port pin.
SLOE
is an input-only output enable with program-
mable polarity (FIFOPINPOLAR.4) for the slave FIFOs
connected to FD[7..0] or FD[15..0].
Multiplexed pin whose function is selected by:
WAKEUP.7 and OEA.3
PA3
is a bidirectional I/O port pin.
WU2
is an alternate source for
USB Wakeup,
enabled
by WU2EN bit (WAKEUP.1) and polarity set by
WU2POL (WAKEUP.4). If the 8051 is in suspend and
WU2EN = 1, a transition on this pin starts up the oscil-
lator and interrupts the 8051 to allow it to exit the
suspend mode. Asserting this pin inhibits the chip from
suspending, if WU2EN=1.
Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA4
is a bidirectional I/O port pin.
FIFOADR0
is an input-only address select for the slave
FIFOs connected to FD[7..0] or FD[15..0].
Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA5
is a bidirectional I/O port pin.
FIFOADR1
is an input-only address select for the slave
FIFOs connected to FD[7..0] or FD[15..0].
Multiplexed pin whose function is selected by the
IFCONFIG[1:0] bits.
PA6
is a bidirectional I/O port pin.
PKTEND
is an input used to commit the FIFO packet
data to the endpoint and whose polarity is program-
mable via FIFOPINPOLAR.5.
Multiplexed pin whose function is selected by the
IFCONFIG[1:0] and PORTACFG.7 bits.
PA7
is a bidirectional I/O port pin.
FLAGD
is a programmable slave-FIFO output status
flag signal.
SLCS#
gates all other slave FIFO enable/strobes
85
70
43
36
PA3 or
WU2
I/O/Z
I
(PA3)
89
71
44
37
PA4 or
FIFOADR0
I/O/Z
I
(PA4)
90
72
45
38
PA5 or
FIFOADR1
I/O/Z
I
(PA5)
91
73
46
39
PA6 or
PKTEND
I/O/Z
I
(PA6)
92
74
47
40
PA7 or
FLAGD or
SLCS#
I/O/Z
I
(PA7)
Port B
44
34
25
18
PB0 or
FD[0]
I/O/Z
I
(PB0)
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB0
is a bidirectional I/O port pin.
FD[0]
is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB1
is a bidirectional I/O port pin.
FD[1]
is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB2
is a bidirectional I/O port pin.
FD[2]
is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB3
is a bidirectional I/O port pin.
FD[3]
is the bidirectional FIFO/GPIF data bus.
45
35
26
19
PB1 or
FD[1]
I/O/Z
I
(PB1)
46
36
27
20
PB2 or
FD[2]
I/O/Z
I
(PB2)
47
37
28
21
PB3 or
FD[3]
I/O/Z
I
(PB3)
Table 4-1. FX2LP Pin Descriptions
(continued)
[10]
128
TQFP
100
TQFP
56
SSOP
56
QFN
Name
Type
Default
Description
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