參數(shù)資料
型號: CY7C64714
廠商: Cypress Semiconductor Corp.
英文描述: EZ-USB FX1 USB Microcontroller Full-speed USB Peripheral Controller(EZ-USB FX1 USB微控制器,全速USB外設控制器)
中文描述: 的EZ - USB FX1的USB微控制器全速USB外設控制器(的EZ - USB FX1的的USB微控制器,全速的USB外設控制器)
文件頁數(shù): 8/50頁
文件大?。?/td> 1419K
代理商: CY7C64714
CY7C64713/14
Document #: 38-08039 Rev. *C
Page 8 of 50
4.12
Endpoint RAM
4.12.1
3 × 64 bytes
8 × 512 bytes (Endpoints 2, 4, 6, 8)
Size
(Endpoints 0 and 1)
4.12.2
EP0—Bidirectional endpoint zero, 64-byte buffer
EP1IN, EP1OUT—64-byte buffers, bulk or interrupt
EP2,4,6,8—Eight 512-byte buffers, bulk, interrupt, or isoch-
ronous, of which only the transfer size is available.
EP4 and EP8 can be double buffered, while EP2 and 6 can
be either double, triple, or quad buffered. Regardless of the
physical size of the buffer, each endpoint buffer accommo-
dates only one full-speed packet. For bulk endpoints the
maximum number of bytes it can accommodate is 64, even
though the physical buffer size is 512 or 1024. For an
ISOCHRONOUS endpoint the maximum number of bytes
it can accommodate is 1023. For endpoint configuration
options, see
Figure 4-5
.
Organization
4.12.3
A separate 8-byte buffer at 0xE6B8-0xE6BF holds the Setup
data from a CONTROL transfer.
Setup Data Buffer
4.12.4
Endpoints 0 and 1 are the same for every configuration.
Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can
be either BULK or INTERRUPT. The endpoint buffers can be
configured in any 1 of the 12 configurations shown in the
vertical columns. In full-speed, BULK mode uses only the first
64 bytes of each buffer, even though memory exists for the
allocation of the isochronous transfers in BULK mode the
unused endpoint buffer space is not available for other opera-
tions. An example endpoint configuration would be:
EP2—1023 double buffered; EP6—64 quad buffered (column 8).
Endpoint Configurations
4.12.5
Default Alternate Settings
4.13
External FIFO Interface
4.13.1
The FX1 slave FIFO architecture has eight 512-byte blocks in
the endpoint RAM that directly serve as FIFO memories, and
are controlled by FIFO control signals (such as IFCLK, SLCS#,
SLRD, SLWR, SLOE, PKTEND, and flags). The usable size of
these buffers depend on the USB transfer mode as described
in Section 4.12.2.
In operation, some of the eight RAM blocks fill or empty from
the SIE, while the others are connected to the I/O transfer
logic. The transfer logic takes two forms, the GPIF for internally
generated control signals, or the slave FIFO interface for
externally controlled transfers.
Architecture
4.13.2
The FX1 endpoint FIFOS are implemented as eight physically
distinct 256x16 RAM blocks. The 8051/SIE can switch any of
the RAM blocks between two domains, the USB (SIE) domain
and the 8051-I/O Unit domain. This switching is done virtually
Master/Slave Control Signals
64
64
64
64
64
1023
1023
1023
1023
1023
1023
1023
64
64
64
64
64
64
64
64
64
64
EP2
EP2
EP2
EP6
EP6
EP8
EP8
EP0 IN&OUT
EP1 IN
EP1 OUT
Figure 4-5. Endpoint Configuration
1023
1023
EP6
1023
64
64
EP8
64
64
EP6
64
64
64
64
EP2
64
64
EP4
64
64
EP2
64
64
EP4
64
64
EP2
64
64
EP4
64
64
EP2
64
64
64
64
EP2
64
64
64
64
EP2
64
64
1023
EP2
1023
1023
EP2
1023
1023
EP2
1023
64
64
EP6
1023
1023
EP6
64
64
EP8
64
64
EP6
64
64
64
64
EP6
1023
1023
EP6
64
64
EP8
64
64
EP6
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
1
2
3
4
5
6
7
8
9
10
11
12
Table 4-6. Default Alternate Settings
[4, 5]
Alternate
Setting
ep0
ep1out
ep1in
ep2
ep4
ep6
ep8
0
1
2
3
64 64
0 64 bulk
0 64 bulk
0 64 bulk out (2×) 64 int out (2×) 64 iso out (2×)
0 64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×)
0 64 bulk in (2×) 64 int in (2×)
0 64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×)
64
64 int
64 int
64
64 int
64 int
64 iso in (2×)
Notes:
4.
5.
“0” means “not implemented.”
“2×” means “double buffered.”
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