參數(shù)資料
型號: CY7C64714
廠商: Cypress Semiconductor Corp.
英文描述: EZ-USB FX1 USB Microcontroller Full-speed USB Peripheral Controller(EZ-USB FX1 USB微控制器,全速USB外設(shè)控制器)
中文描述: 的EZ - USB FX1的USB微控制器全速USB外設(shè)控制器(的EZ - USB FX1的的USB微控制器,全速的USB外設(shè)控制器)
文件頁數(shù): 6/50頁
文件大小: 1419K
代理商: CY7C64714
CY7C64713/14
Document #: 38-08039 Rev. *C
Page 6 of 50
4.9.2
The 8051 puts itself and the rest of the chip into a power-down
mode by setting PCON.0 = 1. This stops the oscillator and
PLL. When WAKEUP is asserted by external logic, the oscil-
lator restarts, after the PLL stabilizes, and then the 8051
receives a wakeup interrupt. This applies whether or not FX1
is connected to the USB.
The FX1 exits the power-down (USB suspend) state using one
of the following methods:
USB bus activity (if D+/D– lines are left floating, noise on
these lines may indicate activity to the FX1 and initiate a
wakeup).
External logic asserts the WAKEUP pin
External logic asserts the PA3/WU2 pin.
The second wakeup pin, WU2, can also be configured as a
general purpose I/O pin. This allows a simple external R-C
network to be used as a periodic wakeup source. Note that
WAKEUP is by default active LOW.
Wakeup Pins
4.10
Program/Data RAM
4.10.1
The FX1 has 16 KBytes of internal program/data RAM, where
PSEN#/RD# signals are internally ORed to allow the 8051 to
access it as both program and data memory. No USB control
registers appear in this space.
Two memory maps are shown in the following diagrams:
Figure 4-3
Internal Code Memory, EA = 0
Figure 4-4
External Code Memory, EA = 1.
Size
4.10.2
This mode implements the internal 16-KByte block of RAM
(starting at 0) as combined code and data memory. When
external RAM or ROM is added, the external read and write
strobes are suppressed for memory spaces that exist inside
the chip. This allows the user to connect a 64-KByte memory
without requiring address decodes to keep clear of internal
memory spaces.
Only the
internal
16 KBytes and
scratch pad
0.5 KBytes RAM
USB download
USB upload
Setup data pointer
I
2
C interface boot load.
Internal Code Memory, EA = 0
4.10.3
The bottom 16 KBytes of program memory is external, and
therefore the bottom 16 KBytes of internal RAM is accessible
only as data memory.
External Code Memory, EA = 1
Table 4-5. Reset Timing Values
Condition
T
RESET
5 ms
Power-On Reset with crystal
Power-On Reset with external
clock
Powered Reset
200
μ
s + Clock stability time
200
μ
s
Figure 4-3. Internal Code Memory, EA = 0
Inside FX1
Outside FX1
7.5 KBytes
USB regs and
4K FIFO buffers
(RD#,WR#)
0.5 KBytes RAM
Data (RD#,WR#)*
(OK to populate
data memory
here—RD#/WR#
strobes are not
active)
40 KBytes
External
Data
Memory
(RD#,WR#)
(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)
16 KBytes RAM
Code and Data
(PSEN#,RD#,WR#)*
48 KBytes
External
Code
Memory
(PSEN#)
(OK to populate
program
memory here—
PSEN# strobe
is not active)
*SUDPTR, USB upload/download, I
2
C interface boot access
FFFF
E200
E1FF
E000
3FFF
0000
Data
Code
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