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參數(shù)資料
| 型號(hào)： | CY7C64013C |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Full-Speed USB (12-Mbps)(全速USB(12-Mbps)) |
| 中文描述： | 全速USB（12 Mbps）的（全速的USB（12 Mbps）的） |
| 文件頁數(shù)： | 32/51頁 |
| 文件大?。?/td> | 2601K |
| 代理商： | CY7C64013C |
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CY7C64013C
CY7C64113C
Document #: 38-08001 Rev. *B
Page 32 of 51
16.7
Each of the GPIO pins can generate an interrupt, if enabled. The interrupt polarity can be programmed for each GPIO port as
part of the GPIO configuration. All of the GPIO pins share a single interrupt vector, which means the firmware needs to read the
GPIO ports with enabled interrupts to determine which pin or pins caused an interrupt. A block diagram of the GPIO interrupt
logic is shown in
Figure 16-4
. Refer to Sections 9.1 and 9.2 for more information of setting GPIO interrupt polarity and enabling
individual GPIO interrupts.
If one port pin has triggered an interrupt, no other port pins can cause a GPIO interrupt until that port pin has returned to its inactive
(non-trigger) state or its corresponding port interrupt enable bit is cleared. The USB Controller does not assign interrupt priority
to different port pins and the Port Interrupt Enable Registers are not cleared during the interrupt acknowledge process.
GPIO/HAPI Interrupt
When HAPI is enabled, the HAPI logic takes over the interrupt vector and blocks any interrupt from the GPIO bits, including
ports/bits not being used by HAPI. Operation of the HAPI interrupt is independent of the GPIO specific bit interrupt enables, and
is enabled or disabled only by bit 5 of the Global Interrupt Enable Register (
Figure 16-1
) when HAPI is enabled. The settings of
the GPIO bit interrupt enables on ports/bits not used by HAPI still effect the CMOS mode operation of those ports/bits. The effect
of modifying the interrupt bits while the Port Config bits are set to “10” is shown in
Table 9-1
. The events that generate HAPI
interrupts are described in Section 14.0.
16.8
The I
2
C interrupt occurs after various events on the I
2
C-compatible bus to signal the need for firmware interaction. This generally
involves reading the I
2
C Status and Control Register (
Figure 13-2
) to determine the cause of the interrupt, loading/reading the
I
2
C Data Register as appropriate, and finally writing the Status and Control Register to initiate the subsequent transaction. The
interrupt indicates that status bits are stable and it is safe to read and write the I
2
C registers. Refer to Section 13.0 for details on
the I
2
C registers.
When enabled, the I
2
C-compatible state machines generate interrupts on completion of the following conditions. The referenced
bits are in the I
2
C Status and Control Register.
1. In
slave receive
mode, after the slave receives a byte of data: The
Addr
bit is set, if this is the first byte since a start or restart
signal was sent by the external master. Firmware must read or write the data register as necessary, then set the
ACK, Xmit
MODE,
and
Continue/Busy
bits appropriately for the next byte.
2. In
slave receive
mode, after a stop bit is detected: The
Received Stop
bit is set, if the stop bit follows a slave receive transaction
where the
ACK
bit was cleared to 0, no stop bit detection occurs.
3. In
slave transmit
mode, after the slave transmits a byte of data: The
ACK
bit indicates if the master that requested the byte
acknowledged the byte. If more bytes are to be sent, firmware writes the next byte into the Data Register and then sets the
Xmit
MODE
and
Continue/Busy
bits as required.
4. In
master transmit
mode, after the master sends a byte of data. Firmware should load the Data Register if necessary, and
set the
Xmit MODE, MSTR MODE
, and
Continue/Busy
bits appropriately. Clearing the
MSTR MODE
bit issues a stop signal
to the I
2
C-compatible bus and return to the idle state.
I
2
C Interrupt
Figure 16-4. GPIO Interrupt Structure
Port
Register
OR Gate
(1 input per
GPIO pin)
GPIO Interrupt
Flip Flop
CLR
GPIO
Pin
1 = Enable
0 = Disable
Port Interrupt
Enable Register
1 = Enable
0 = Disable
Interrupt
Priority
Encoder
IRQout
Interrupt
Vector
D
Q
M
U
X
1
Global
GPIO Interrupt
Enable
(Bit 5, Register 0x20)
IRA
Configuration
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C64013C-PXC | 功能描述:IC MCU 8K FULL SPEED USB 28DIP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:M8™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標(biāo)準(zhǔn)包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲(chǔ)器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
| CY7C64013C-SXC | 功能描述:8位微控制器 -MCU Full Spd USB 12-Mbps Function RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CY7C64013C-SXCT | 功能描述:8位微控制器 -MCU Full Spd USB 12-Mbps Function RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CY7C64013-SC | 功能描述:IC MCU 8K FULL SPEED USB 28SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:M8™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標(biāo)準(zhǔn)包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲(chǔ)器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
| CY7C64013-SXC | 制造商:Cypress Semiconductor 功能描述:8BIT MCU USB SMD 64013 SOIC28 |
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