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參數(shù)資料
| 型號： | CY7C64013C |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Full-Speed USB (12-Mbps)(全速USB(12-Mbps)) |
| 中文描述： | 全速USB（12 Mbps）的（全速的USB（12 Mbps）的） |
| 文件頁數(shù)： | 30/51頁 |
| 文件大?。?/td> | 2601K |
| 代理商： | CY7C64013C |
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CY7C64013C
CY7C64113C
Document #: 38-08001 Rev. *B
Page 30 of 51
The interrupt controller contains a separate flip-flop for each interrupt. See
Figure 16-3
for the logic block diagram of the interrupt
controller. When an interrupt is generated, it is first registered as a pending interrupt. It stays pending until it is serviced or a reset
occurs. A pending interrupt only generates an interrupt request if it is enabled by the corresponding bit in the interrupt enable
registers. The highest priority interrupt request is serviced following the completion of the currently executing instruction.
When servicing an interrupt, the hardware does the following
1. Disables all interrupts by clearing the Global Interrupt Enable bit in the CPU (the state of this bit can be read at Bit 2 of the
Processor Status and Control Register,
Figure 15-1
).
2. Clears the flip-flop of the current interrupt.
3. Generates an automatic CALL instruction to the ROM address associated with the interrupt being serviced (i.e., the Interrupt
Vector, see Section 16.1).
The instruction in the interrupt table is typically a JMP instruction to the address of the Interrupt Service Routine (ISR). The user
can re-enable interrupts in the interrupt service routine by executing an EI instruction. Interrupts can be nested to a level limited
only by the available stack space.
The Program Counter value as well as the Carry and Zero flags (CF, ZF) are stored onto the Program Stack by the automatic
CALL instruction generated as part of the interrupt acknowledge process. The user firmware is responsible for ensuring that the
processor state is preserved and restored during an interrupt. The PUSH A instruction should typically be used as the first
command in the ISR to save the accumulator value and the POP A instruction should be used to restore the accumulator value
just before the RETI instruction. The program counter CF and ZF are restored and interrupts are enabled when the RETI
instruction is executed.
The DI and EI instructions can be used to disable and enable interrupts, respectively. These instructions affect only the Global
Interrupt Enable bit of the CPU. If desired, EI can be used to re-enable interrupts while inside an ISR, instead of waiting for the
RETI that exists the ISR. While the global interrupt enable bit is cleared, the presence of a pending interrupt can be detected by
examining the IRQ Sense bit (Bit 7 in the Processor Status and Control Register).
16.1
The Interrupt Vectors supported by the USB Controller are listed in
Table 16-1
. The lowest-numbered interrupt (USB Bus Reset
interrupt) has the highest priority, and the highest-numbered interrupt (I
2
C interrupt) has the lowest priority.
Interrupt Vectors
Although Reset is not an interrupt, the first instruction executed after a reset is at PROM address 0x0000h—which corresponds
to the first entry in the Interrupt Vector Table. Because the JMP instruction is two bytes long, the interrupt vectors occupy two bytes.
CLR
Global
Interrupt
Enable
Bit
Interrupt
Acknowledge
IRQout
USB Reset ClearInterrupt
Interrupt Priority Encoder
Enable [0]
(Reg 0x20)
D
Q
1
CLR
USB Reset IRQ
128-
μ
s CLR
128-
μ
s IRQ
1-ms CLR
1-ms IRQ
AddrA EP0 CLR
AddrA EP0 IRQ
AddrA EP1 CLR
I
2
C IRQ
Vector
Enable [6]
(Reg 0x20)
CLK
CLR
D
Q
CLK
1
I
2
C CLR
I
2
C Int
USB Reset Int
AddrA EP1 IRQ
AddrA EP2 CLR
IRQ Sense
IRQ
Controlled by DI, EI, and
RETI Instructions
DAC IRQ
DAC CLR
To CPU
CPU
GPIO IRQ
GPIO CLR
Hub IRQ
Hub CLR
AddrA EP2 IRQ
AddrB EP0 CLR
AddrB EP0 IRQ
AddrB EP1 CLR
AddrB EP1 IRQ
CLR
D
Enable [2]
(Reg 0x21)
Q
1
CLK
AddrA ENP2 Int
Int Enable
Sense
Figure 16-3. Interrupt Controller Function Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C64113C | Full-Speed USB (12-Mbps)(全速USB(12-Mbps)) |
| CY7C64013 | Full-Speed USB (12 Mbps) Function(全速 USB (12 Mbps)性能) |
| CY7C64113 | Full-Speed USB (12 Mbps) Function(全速 USB (12 Mbps)性能) |
| CY7C64713 | EZ-USB FX1 USB Microcontroller Full-speed USB Peripheral Controller(EZ-USB FX1 USB微控制器，全速USB外設(shè)控制器) |
| CY7C64714 | EZ-USB FX1 USB Microcontroller Full-speed USB Peripheral Controller(EZ-USB FX1 USB微控制器，全速USB外設(shè)控制器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C64013C-PXC | 功能描述:IC MCU 8K FULL SPEED USB 28DIP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:M8™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標(biāo)準(zhǔn)包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
| CY7C64013C-SXC | 功能描述:8位微控制器 -MCU Full Spd USB 12-Mbps Function RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CY7C64013C-SXCT | 功能描述:8位微控制器 -MCU Full Spd USB 12-Mbps Function RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CY7C64013-SC | 功能描述:IC MCU 8K FULL SPEED USB 28SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:M8™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標(biāo)準(zhǔn)包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
| CY7C64013-SXC | 制造商:Cypress Semiconductor 功能描述:8BIT MCU USB SMD 64013 SOIC28 |
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