參數(shù)資料
型號(hào)： CY7C63743-SC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
中文描述： 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO24
封裝： 0.300 INCH, PLASTIC, MO-119, SOIC-24
文件頁(yè)數(shù)： 39/58頁(yè)
文件大?。?/td> 1236K
代理商： CY7C63743-SC
FOR
FOR
enCoRe
USB CY7C63722/23
CY7C63743
Document #: 38-08022 Rev. **
Page 39 of 58
Bit 1: 128-
μ
s Interrupt Enable
The 128-
μ
s interrupt is another source of timer interrupt from the free-running timer. The user should disable both timer
interrupts (128-
μ
s and 1.024-ms) before going into the suspend mode to avoid possible conflicts between servicing the timer
interrupts first or the suspend request first when waking up.
1 = Enable. Periodic interrupts will be generated approximately every 128
μ
s.
0 = Disable.
Bit 0: USB Bus Reset - PS/2 Interrupt Enable
The function of this interrupt is selectable between detection of either a USB bus reset condition, or PS/2 activity. The selection
is made with the USB-PS/2 Interrupt Mode bit in the USB Status and Control Register (
Figure 13-1
). In either case, the interrupt
will occur if the selected condition exists for 256
μ
s, and may occur as early as 128
μ
s.
A USB bus reset is indicated by a single ended zero (SE0) on the USB D+ and D– pins. The USB Bus Reset interrupt occurs
when the SE0 condition ends. PS/2 activity is indicated by a continuous LOW on the SDATA pin. The PS/2 interrupt occurs
as soon as the long LOW state is detected.
During the entire interval of a USB Bus Reset or PS/2 interrupt event, the USB Device Address register is cleared.
The Bus Reset/PS/2 interrupt may occur 128
μ
s after the bus condition is removed.
1 = Enable
0 = Disable
Bit [7:3]:
Reserved.
Bit [2:1]: EP2,1 Interrupt Enable
There are two non-control endpoint (EP2 and EP1) interrupts. If enabled, a non-control endpoint interrupt is generated when:
The USB host writes valid data to an endpoint FIFO. However, if the endpoint is in ACK OUT modes, an interrupt is generated
regardless of data packet validity (i.e., good CRC). Firmware must check for data validity.
The device SIE sends a NAK or STALL handshake packet to the USB host during the host attempts to read data from the
endpoint (INs).
The device receives an ACK handshake after a successful read transaction (IN) from the host.
The device SIE sends a NAK or STALL handshake packet to the USB host during the host attempts to write data (OUTs)
to the endpoint FIFO.
1 = Enable
0 = Disable
Refer to
Table 22-1
for more information.
Bit 0: EP0 Interrupt Enable
If enabled, a control endpoint interrupt is generated when:
The endpoint 0 mode is set to accept a SETUP token.
After the SIE sends a 0-byte packet in the status stage of a control transfer.
The USB host writes valid data to an endpoint FIFO. However, if the endpoint is in ACK OUT modes, an interrupt is generated
regardless of what data is received. Firmware must check for data validity.
The device SIE sends a NAK or STALL handshake packet to the USB host during the host attempts to read data from the
endpoint (INs).
The device SIE sends a NAK or STALL handshake packet to the USB host during the host attempts to write data (OUTs)
to the endpoint FIFO.
1 = Enable EP0 interrupt
0 = Disable EP0 interrupt
Bit #
7
6
5
4
3
2
1
0
Bit Name
Reserved
EP2
Interrupt
Enable
EP1
Interrupt
Enable
EP0
Interrupt
Enable
Read/Write
-
-
-
-
-
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Figure 21-2. Endpoint Interrupt Enable Register (Address 0x21)
相關(guān)PDF資料
PDF描述
CY7C63722 enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63723 enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63723-PC enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63743 enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63743-PC enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C63743-SXC 功能描述:IC MCU 8K USB/PS2 LS 24SOIC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:enCoRe™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標(biāo)準(zhǔn)包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲(chǔ)器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382
CY7C63743-SXCT 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
CY7C63801-PXC 功能描述:USB 接口集成電路 4K Flash 256 byte RAM COM RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
CY7C63801-SXC 功能描述:USB 接口集成電路 USB Peripheral Cntrl 4K/256 16-SOIC RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
CY7C63801-SXCES 制造商:Cypress Semiconductor 功能描述:
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