參數(shù)資料
型號: CY7C63743-SC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
中文描述: 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO24
封裝: 0.300 INCH, PLASTIC, MO-119, SOIC-24
文件頁數(shù): 21/58頁
文件大小: 1236K
代理商: CY7C63743-SC
FOR
FOR
enCoRe
USB CY7C63722/23
CY7C63743
Document #: 38-08022 Rev. **
Page 21 of 58
Hi-Z Mode
(Mode1 = 0 and Mode0 = 0)
Q1, Q2, and Q3 (
Figure 12-1
) are OFF. The GPIO pin is not driven internally. Performing a read from the Port Data Register
return the actual logic value on the port pins.
Low Sink Mode
(Mode1 = 1, Mode0 = 0, and the pin’s Data Register = 0)
Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of sinking 2 mA of current.
Medium Sink Mode
(Mode1 = 0, Mode0 = 1, and the pin’s Data Register = 0)
Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of sinking 8 mA of current.
High Sink Mode
(Mode1 = 1, Mode0 = 1, and the pin’s Data Register = 0)
Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of sinking 50 mA of current.
High Drive Mode
(Mode1 = 0 or 1, Mode0 = 1, and the pin’s Data Register = 1)
Q1 and Q2 are OFF. Q3 is ON. The GPIO pin is capable of sourcing 2 mA of current.
Resistive Mode
(Mode1 = 1, Mode0 = 0, and the pin’s Data Register = 1)
Q2 and Q3 are OFF. Q1 is ON. The GPIO pin is pulled up with an internal 14-k
resistor.
Note that open drain mode can be achieved by fixing the Data and Mode1 Registers LOW, and switching the Mode0 register.
Input thresholds are CMOS, or TTL as shown in the table (See Section 25.0 for the input threshold voltage in TTL or CMOS
modes). Both input modes include hysteresis to minimize noise sensitivity. In suspend mode, if a pin is used for a wake-up
interrupt using an external R-C circuit, CMOS mode is preferred for lowest power.
12.1
Port 2 serves as an auxiliary input port as shown in
Figure 12-8
. The Port 2 inputs all have TTL input thresholds.
Auxiliary Input Port
Bit [7:6]:
Reserved
Bit [5:4]: D+ (SCLK) and D– (SDATA) States
The state of the D+ and D– pins can be read at Port 2 Data Register. Performing a read from the port pins returns their logic
values.
1 = Port Pin is logic HIGH
0 = Port Pin is logic LOW
Table 12-1. Ports 0 and 1 Output Control Truth Table
Data Register
Mode1
Mode0
Output Drive Strength
Input Threshold
0
0
0
Hi-Z
CMOS
1
Hi-Z
TTL
0
0
1
Medium (8 mA) Sink
CMOS
1
High Drive
CMOS
0
1
0
Low (2 mA) Sink
CMOS
1
Resistive
CMOS
0
1
1
High (50 mA) Sink
CMOS
1
High Drive
CMOS
Bit #
7
6
5
4
3
2
1
0
Bit Name
Reserved
D+ (SCLK)
State
D– (SDATA)
State
Reserved
P2.1
(Internal
Clock Mode
Only)
P2.0
VREG Pin
State
Read/Write
-
-
R
R
-
-
R
R
Reset
0
0
0
0
0
0
0
0
Figure 12-8. Port 2 Data Register (Address 0x02)
相關PDF資料
PDF描述
CY7C63722 enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63723 enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63723-PC enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63743 enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
CY7C63743-PC enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller
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