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參數(shù)資料
| 型號： | CY7C63221A-XC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | TV 32C 32#20 SKT RECP |
| 中文描述： | 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, UUC18 |
| 封裝： | DIE-18 |
| 文件頁數(shù)： | 32/49頁 |
| 文件大?。?/td> | 960K |
| 代理商： | CY7C63221A-XC |
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FOR
FOR
enCoRe
USB
CY7C63221/31A
Document #: 38-08028 Rev. *A
Page 32 of 49
19.2
Interrupt latency can be calculated from the following equation:
Interrupt Latency =
(Number of clock cycles remaining in the current instruction) + (10 clock cycles for the CALL instruction) +
(5 clock cycles for the JMP instruction)
For example, if a 5-clock-cycle instruction such as JC is being executed when an interrupt occurs, the first instruction of the
Interrupt Service Routine will execute a minimum of 16 clocks (1+10+5) or a maximum of 20 clocks (5+10+5) after the interrupt
is issued. With a 6 MHz external resonator, internal CPU clock speed is 12 MHz, so 20 clocks take 20/12 MHz = 1.67
μ
s.
Interrupt Latency
19.3
The following sections provide details on the different types of interrupt sources.
Interrupt Sources
Bit 7: Wake-up Interrupt Enable
The internal wake-up timer is normally used to wake the part from suspend mode, but it can also provide an interrupt when
the part is awake. The wake-up timer is cleared whenever the Wake-up Interrupt Enable bit is written to a 0, and runs whenever
that bit is written to a 1. When the interrupt is enabled, the wake-up timer provides periodic interrupts at multiples of period,
as described in Section 11.2.
1 = Enable wake-up timer for periodic wake-up.
0 = Disable and power-off wake-up timer.
Bit 6: GPIO Interrupt Enable
Each GPIO pin can serve as an interrupt input. During a reset, GPIO interrupts are disabled by clearing all GPIO interrupt
enable registers. Writing a
‘
1
’
to a GPIO Interrupt Enable bit enables GPIO interrupts from the corresponding input pin. These
registers are shown in
Figure 19-4
for Port 0 and
Figure 19-5
for Port 1. In addition to enabling the desired individual pins for
interrupt, the main GPIO interrupt must be enabled, as explained in Section 19.0.
The polarity that triggers an interrupt is controlled independently for each GPIO pin by the GPIO Interrupt Polarity Registers.
Setting a Polarity bit to
‘
0
’
allows an interrupt on a falling GPIO edge, while setting a Polarity bit to
‘
1
’
allows an interrupt on a
rising GPIO edge. The Polarity Registers reset to 0 and are shown in
Figure 19-6
for Port 0 and
Figure 19-7
for Port 1.
All of the GPIO pins share a single interrupt vector, which means the firmware will need to read the GPIO ports with enabled
interrupts to determine which pin or pins caused an interrupt.The GPIO interrupt structure is illustrated in
Figure 19-8
.
Note that if one port pin triggered an interrupt, no other port pins can cause a GPIO interrupt until that port pin has returned
to its inactive (non-trigger) state or its corresponding port interrupt enable bit is cleared. The CY7C63221/31A does not assign
interrupt priority to different port pins and the Port Interrupt Enable Registers are not affected by the interrupt acknowledge
process.
1 = Enable
0 = Disable
Bit [5:3]:
Reserved
Bit 2: 1.024-ms Interrupt Enable
The 1.024-ms interrupts are periodic timer interrupts from the free-running timer (based on the 6-MHz clock). The user should
disable this interrupt before going into the suspend mode to avoid possible conflicts between servicing the timer interrupts
(128-
μ
s interrupt and 1.024-ms interrupt) first or the suspend request first when waking up.
1 = Enable. Periodic interrupts will be generated approximately every 1.024 ms.
0 = Disable.
Bit #
Bit Name
7
6
5
4
3
2
1
0
Wake-up
Interrupt
Enable
GPIO
Interrupt
Enable
Reserved
1.024-ms
Interrupt
Enable
128-
μ
s
Interrupt
Enable
USB Bus
Reset /
PS/2 Activity
Intr. Enable
R/W
0
Read/Write
Reset
R/W
0
R/W
0
-
0
-
0
-
0
R/W
0
R/W
0
Figure 19-1. Global Interrupt Enable Register (Address 0x20)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C63231A | enCoRe USB Low-speed USB Peripheral Controller(enCoRe USB 低速USB外設(shè)控制器) |
| CY7C64013C | Full-Speed USB (12-Mbps)(全速USB(12-Mbps)) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C63231A-PXC | 功能描述:8位微控制器 -MCU enCoRe RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CY7C63231A-SC | 功能描述:IC MCU 3K USB LS PERIPH 18-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:enCoRe™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標(biāo)準(zhǔn)包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
| CY7C63231A-SXC | 功能描述:8位微控制器 -MCU enCoRe RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CY7C63231A-SXCT | 功能描述:IC MCU 3K USB LS PERIPH 18-SOIC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:enCoRe™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標(biāo)準(zhǔn)包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
| CY7C63310-PXC | 功能描述:USB 接口集成電路 USB 3K Flash 128 byte RAM COM RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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