參數(shù)資料
型號(hào): CY7C63221A-XC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: TV 32C 32#20 SKT RECP
中文描述: 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, UUC18
封裝: DIE-18
文件頁(yè)數(shù): 23/49頁(yè)
文件大?。?/td> 960K
代理商: CY7C63221A-XC
FOR
FOR
enCoRe
USB
CY7C63221/31A
Document #: 38-08028 Rev. *A
Page 23 of 49
13.1
A typical USB enumeration sequence is shown below. In this description,
Firmware
refers to embedded firmware in the
CY7C632XX controller.
1. The host computer sends a SETUP packet followed by a DATA packet to USB address 0 requesting the Device descriptor.
2. Firmware decodes the request and retrieves its Device descriptor from the program memory tables.
3. The host computer performs a control read sequence and Firmware responds by sending the Device descriptor over the USB
bus, via the on-chip FIFO.
4. After receiving the descriptor, the host sends a SETUP packet followed by a DATA packet to address 0 assigning a new USB
address to the device.
5. Firmware stores the new address in its USB Device Address Register after the no-data control sequence completes.
6. The host sends a request for the Device descriptor using the new USB address.
7. Firmware decodes the request and retrieves the Device descriptor from program memory tables.
8. The host performs a control read sequence and Firmware responds by sending its Device descriptor over the USB bus.
9. The host generates control reads from the device to request the Configuration and Report descriptors.
10.Once the device receives a Set Configuration request, its functions may now be used.
11.Firmware should take appropriate action for Endpoint 1 transactions, which may occur from this point.
USB Enumeration
13.2
USB status and control is regulated by the USB Status and Control Register as shown in
Figure 13-1
.
USB Port Status and Control
Bit 7: PS/2 Pull-up Enable
This bit is used to enable the internal PS/2 pull-up resistors on the SDATA and SCLK pins. Normally the output high level on
these pins is V
CC
, but note that the output will be clamped to approximately 1 Volt above V
REG
if the VREG Enable bit is set,
or if the Device Address is enabled (bit 7 of the USB Device Address Register,
Figure 14-1
).
1 = Enable PS/2 pull-up resistors. The SDATA and SCLK pins are pulled up internally to V
CC
with two resistors of approximately
5 k
(see Section 23.0 for the value of R
PS2
).
0 = Disable PS/2 pull-up resistors.
Bit 6: VREG Enable
A 3.3V voltage regulator is integrated on chip to provide a voltage source for a 1.5-k
pull-up resistor connected to the D
pin
as required by the USB Specification. Note that the VREG output has an internal series resistance of approximately 200
, the
external pull-up resistor required is approximately 1.3-k
(see
Figure 16-1
).
1 = Enable the 3.3V output voltage on the VREG pin.
0 = Disable. The VREG pin can be configured as an input.
Bit 5: USB-PS/2 Interrupt Select
This bit allows the user to select whether an USB bus reset interrupt or a PS/2 activity interrupt will be generated when the
interrupt conditions are detected.
1 = PS/2 interrupt mode. A PS/2 activity interrupt will occur if the SDATA pin is continuously LOW for 128 to 256
μ
s.
0 = USB interrupt mode (default state). In this mode, a USB bus reset interrupt will occur if the single ended zero (SE0, D
and D+ are LOW) exists for 128 to 256
μ
s.
See Section 19.0 for more details.
Bit 4:
Reserved. Must be written as a
0
.
Bit #
Bit Name
7
6
5
4
3
2
1
0
PS/2 Pull-up
Enable
VREG
Enable
USB Reset-
PS/2 Activity
Interrupt
Mode
R/W
0
Reserved
USB
Bus Activity
D+/D- Forcing Bit
Read/Write
Reset
R/W
0
R/W
0
-
0
R/W
0
R/W
0
R/W
0
R/W
0
Figure 13-1. USB Status and Control Register (Address 0x1F)
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