參數(shù)資料
型號(hào)： CY7C43682
廠商： Cypress Semiconductor Corp.
英文描述： 16K x36 x2 Bidirectional Synchronous FIFO(16K x36 x2 雙向同步先進(jìn)先出)
中文描述： 16K的x36 x2雙向同步FIFO（16K的x36 x2雙向同步先進(jìn)先出）
文件頁(yè)數(shù)： 25/31頁(yè)
文件大?。?/td> 463K
代理商： CY7C43682
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
25
PRELIMINARY
Signal Description
Reset (RST1, RST2)
Each of the two FIFO memories of the CY7C436X2 undergoes
a complete reset by taking its associated Master Reset (RST1,
RST2) input LOW for at least four Port A clock (CLKA) and four
Port B clock (CLKB) LOW-to-HIGH transitions. The Master Re-
set inputs can switch asynchronously to the clocks. A Master
Reset initializes the internal read and write pointers and forces
the Full/Input Ready flag (FFA/IRA, FFB/IRB) LOW, the Empty/
Output Ready flag (EFA/ORA, EFB/ORB) LOW, the Almost
Empty flag (AEA, AEB) LOW, and the Almost Full flag (AFA,
AFB) HIGH. A Master Reset also forces the Mailbox flag
(MBF1, MBF2) of the parallel mailbox register HIGH. After a
Master Reset, the FIFO
’
s Full/Input Ready flag is set HIGH
after two clock cycles to begin normal operation. A Master
Reset must be performed on the FIFO after power-up, before
data is written to its memory.
A LOW-to-HIGH transition on a FIFO reset (RST1, RST2) in-
put latches the values of the Flag select (FS0, FS1) for choos-
ing the Almost Full and Almost Empty offset programming
method (see Almost Empty and Almost Full flag offset pro-
gramming below).
First-Word Fall-Through (FWFT/STAN)
After Master Reset, the FWFT select function is active, permit-
ting a choice between two possible timing modes: CY
Standard Mode or First-Word Fall-Through (FWFT) Mode.
Once the Master Reset (RST1, RST2) input is HIGH, a HIGH
on the FWFT/STAN input during the next LOW-to-HIGH tran-
sition of CLKA (for FIFO1) and CLKB (for FIFO2) will select
CY Standard Mode. This mode uses the Empty Flag function
(EFA, EFB) to indicate whether or not there are any words
present in the FIFO memory. It uses the Full Flag function
(FFA, FFB) to indicate whether or not the FIFO memory has
any free space for writing. In CY Standard mode, every word
read from the FIFO, including the first, must be requested us-
ing a formal read operation.
Once the Master Reset (RST1, RST2) input is HIGH, a LOW
on the FWFT/STAN input during the next LOW-to-HIGH tran-
sition of CLKA (for FIFO1) and CLKB (for FIFO2) will select
FWFT Mode. This mode uses the Output Ready function
(ORA, ORB) to indicate whether or not there is valid data at
the data outputs (A
0
–
35
or B
0
–
35
). It also uses the Input Ready
function (IRA, IRB) to indicate whether or not the FIFO mem-
ory has any free space for writing. In the FWFT mode, the first
word written to an empty FIFO goes directly to data outputs,
no read request necessary. Subsequent words must be ac-
cessed by performing a formal read operation.
Following Master Reset, the level applied to the FWFT/STD
input to choose the desired timing mode must remain static
throughout the FIFO operation.
Programming the Almost Empty and Almost Full Flags
Four registers in the CY7C436X2 are used to hold the offset
values for the Almost Empty and Almost Full flags. The Port B
Almost Empty flag (AEB) offset register is labeled X1 and the
Port A Almost Empty flag (AEA) offset register is labeled X2.
The Port A Almost Full flag (AFA) offset register is labeled Y1
and the Port B Almost Full flag (AFB) offset register is labeled
Y2. The index of each register name corresponds with preset
values during the reset of a FIFO, programmed in parallel us-
ing the FIFO
’
s Port A data inputs (see
Table 1
).
To program the X1, X2, Y1, and Y2 registers from Port A, per-
form a Master Reset on both FIFOs simultaneously with FS0
and FS1 LOW during the LOW-to-HIGH transition of RST1 and
RST2. After this reset is complete, the first four writes to FIFO1
do not store data in RAM but load the offset registers in the
order Y1, X1, Y2, X2. The Port A data inputs used by the offset
registers are (A
0
–
7
), (A
0
–
8
), (A
0
–
9
), (A
0
–
11
), or (A
0
–
13
), for the
CY7C436X2, respectively. The highest numbered input is
used as the most significant bit of the binary number in each
case. Valid programming values for the registers range from 1
to 252 for the CY7C43622; 1 to 508 for the CY7C43632; 1 to
1012 for the CY7C43642; 1 to 4092 for the CY7C43662; 1 to
16380 for the CY7C43682. After all the offset registers are
programmed from Port A, the Port B Full/Input Ready (FFB/
IRB) is set HIGH and both FIFOs begin normal operation.
FS0 and FS1 function the same way in both CY Standard and
FWFT modes.
FIFO Write/Read Operation
The state of the Port A data (A
0
–
35
) lines is controlled by Port
A Chip Select (CSA) and Port A Write/Read Select (W/RA).
The A
0
–
35
lines are in the high-impedance state when either
CSA or W/RA is HIGH. The A
0
–
35
lines are active outputs
when both CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A
0
–
35
inputs on a LOW-to-
HIGH transition of CLKA when CSA is LOW, W/RA is HIGH,
ENA is HIGH, MBA is LOW, and FFA/IRA is HIGH. Data is read
from FIFO2 to the A
0
–
35
outputs by a LOW-to-HIGH transition
of CLKA when CSA is LOW, W/RA is LOW, ENA is HIGH,
MBA is LOW, and EFA/ORA is HIGH (see
Table 2
). FIFO reads
and writes on Port A are independent of any concurrent Port
B operation.
The Port B control signals are identical to those of Port A with
the exception that the Port B Write/Read select (W/RB) is the
inverse of the Port A Write/Read Select (W/RA). The state of
the Port B data (B
0
–
35
) lines is controlled by the Port B Chip
Select (CSB) and Port B Write/Read Select (W/RB).The B
0
–
35
lines are in the high-impedance state when either CSB is
HIGH or W/RB is LOW. The B
0
–
35
lines are active outputs
when CSB is LOW and W/RB is HIGH.
Data is loaded into FIFO2 from the B
0
–
35
inputs on a LOW-to-
HIGH transition of CLKB when CSB is LOW, W/RB is LOW,
ENB is HIGH, MBB is LOW, and FFB/IRB is HIGH. Data is read
from FIFO1 to the B
0
–
35
outputs by a LOW-to-HIGH transition
of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH,
MBB is LOW, and EFB/ORB is HIGH (see
Table 3
). FIFO reads
and writes on Port B are independent of any concurrent Port
A operation.
The set-up and hold time constraints to the port clocks for the
port Chip Selects and Write/Read Selects are only for enabling
write and read operations and are not related to high-imped-
ance control of the data outputs. If a port enable is LOW during
a clock cycle, the port
’
s Chip Select and Write/Read select
may change states during the set-up and hold time window of
the cycle.
When operating the FIFO in FWFT Mode and the Output
Ready flag is LOW, the next word written is automatically sent
to the FIFO
’
s output register by the LOW-to-HIGH transition of
the port clock that sets the Output Ready flag HIGH, data re-
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