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參數(shù)資料
| 型號： | CY7C43663AV |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 4K x36 單向同步先進(jìn)先出帶總線匹配) |
| 中文描述： | 3.3 4K的x36單向同步FIFO瓦特/總線匹配（3.3 4K的x36單向同步先進(jìn)先出帶總線匹配） |
| 文件頁數(shù)： | 22/28頁 |
| 文件大?。?/td> | 420K |
| 代理商： | CY7C43663AV |
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CY7C43643AV
CY7C43663AV/CY7C43683AV
22
PRELIMINARY
synchronizing clock. Therefore, an Empty flag is LOW if a word
in memory is the next data to be sent to the FIFO output reg-
ister and two cycles have not elapsed since the time the word
was written. The Empty flag of the FIFO remains LOW until the
second LOW-to-HIGH transition of the synchronizing clock oc-
curs, forcing the Empty flag HIGH; only then can data be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag
synchronizing clock begins the first synchronization cycle of a
write if the clock transition occurs at time t
SKEW1
or greater
after the write. Otherwise, the subsequent clock cycle can be
the first synchronization cycle.
Full/Input Ready Flags (FF/IR)
This is a dual-purpose flag. In FWFT Mode, the Input Ready
(IR) function is selected. In CY Standard Mode, the Full Flag
(FF) function is selected. For both timing modes, when the
Full/Input Ready flag is HIGH, a memory location is free in the
SRAM to receive new data. No memory locations are free
when the Full/Input Ready flag is LOW and attempted writes
to the FIFO are ignored.
The Full/Input Ready flag of a FIFO is synchronized to the port
clock that writes data to its array. For both FWFT and CY Stan-
dard modes, each time a word is written to a FIFO, its write
pointer is incremented. The state machine that controls a Full/
Input Ready flag monitors a write pointer and read pointer
comparator that indicates when the FIFO SRAM status is full,
full
–
1, or full
–
2. From the time a word is read from a FIFO, its
previous memory location is ready to be written to in a mini-
mum of two cycles of the Full/Input Ready flag synchronizing
clock. Therefore, a Full/Input Ready flag is LOW if less than
two cycles of the Full/Input Ready flag synchronizing clock
have elapsed since the next memory write location has been
read. The second LOW-to-HIGH transition on the Full/Input
Ready flag synchronizing clock after the read sets the Full/
Input Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchro-
nizing clock begins the first synchronization cycle of a read if
the clock transition occurs at time t
SKEW1
or greater after the
read. Otherwise, the subsequent clock cycle can be the first
synchronization cycle.
Almost Empty Flags (AE)
The Almost Empty flag of a FIFO is synchronized to the port
clock that reads data from its array. The state machine that
controls an Almost Empty flag monitors a write pointer and
read pointer comparator that indicates when the FIFO SRAM
status is almost empty, almost empty+1, or almost empty+2.
The Almost Empty state is defined by the contents of register
X for AE. These registers are loaded with preset values during
a FIFO reset, programmed from Port A, or programmed seri-
ally (see Almost Empty flag and Almost Full flag offset pro-
gramming above). An Almost Empty flag is LOW when its FIFO
contains X or less words and is HIGH when its FIFO contains
(X+1) or more words. A data word present in the FIFO output
register has been read from memory.
Two LOW-to-HIGH transitions of the Almost Empty flag syn-
chronizing clock are required after a FIFO write for its Almost
Empty flag to reflect the new level of fill. Therefore, the Almost
Full flag of a FIFO containing (X+1) or more words remains
LOW if two cycles of its synchronizing clock have not elapsed
since the write that filled the memory to the (X+1) level. An
Almost Empty flag is set HIGH by the second LOW-to-HIGH
transition of its synchronizing clock after the FIFO write that
fills memory to the (X+1) level. A LOW-to-HIGH transition of an
Almost Empty flag synchronizing clock begins the first syn-
chronization cycle if it occurs at time t
SKEW2
or greater after
the write that fills the FIFO to (X+1) words. Otherwise, the sub-
sequent synchronizing clock cycle may be the first synchroni-
zation cycle.
Almost Full Flags (AF)
The Almost Full flag of a FIFO is synchronized to the port clock
that writes data to its array. The state machine that controls an
Almost Full flag monitors a write pointer and read pointer com-
parator that indicates when the FIFO SRAM status is almost
full, almost full
–
1, or almost full
–
2. The Almost Full state is
defined by the contents of register Y for AF. These registers
are loaded with preset values during a FIFO reset, pro-
grammed from Port A, or programmed serially (see Almost
Empty flag and Almost Full flag offset programming above). An
Almost Full flag is LOW when the number of words in its FIFO
is greater than or equal to (1024
–
Y), (4096
–
Y), or (16384
–
Y),
for the CY7C436X3AV respectively. An Almost Full flag is
HIGH when the number of words in its FIFO is less than or
equal to [1024
–
(Y+1)], [4096
–
(Y+1)], or [16384
–
(Y+1)], for the
CY7C436X3AV respectively. Note that a data word present in
the FIFO output register has been read from memory.
Two LOW-to-HIGH transitions of the Almost Full flag synchro-
nizing clock are required after a FIFO read for its Almost Full
flag to reflect the new level of fill. Therefore, the Almost Full
flag of a FIFO containing [1024/4096/16384
–
(Y+1)] or less
words remains LOW if two cycles of its synchronizing clock
have not elapsed since the read that reduced the number of
words in memory to [1024/4096/16384
–
(Y+1)]. An Almost Full
flag is set HIGH by the second LOW-to-HIGH transition of its
synchronizing clock after the FIFO read that reduces the num-
ber of words in memory to [1024/4096/16384
–
(Y+1)]. A LOW-
to-HIGH transition of an Almost Full flag synchronizing clock
begins the first synchronization cycle if it occurs at time t
SKEW2
or greater after the read that reduces the number of words in
memory to [1024/4096/16384
–
(Y+1)]. Otherwise, the subse-
quent synchronizing clock cycle may be the first synchroniza-
tion cycle.
Mailbox Registers
Each FIFO has a 36-bit bypass register to pass command and
control information between Port A and Port B without putting
it in queue. The Mailbox Select (MBA, MBB) inputs choose
between a mail register and a FIFO for a port data transfer
operation. The usable width of both the Mail1 and Mail2 regis-
ters matches the selected bus size for Port B.
A LOW-to-HIGH transition on CLKA writes A
0
35
data to the
Mail1 Register when a Port A write is selected by CSA, W/RA,
and ENA with MBA HIGH. If the selected Port A bus size is
also 36 bits, then the usable width of the Mail1 Register em-
ploys data lines A
0
35
. If the selected Port A bus size is 18 bits,
then the usable width of the Mail1 Register employs data lines
A
0
17
. (In this case, A
18
35
are don
’
t care inputs.) If the select-
ed Port A bus size is 9 bits, then the usable width of the Mail1
Register employs data lines A
0
–
8
. (In this case, A
9
35
are
“
Don
’
t Care
”
inputs.)
A LOW-to-HIGH transition on CLKB writes B
0
35
data to the
Mail2 Register when a Port B write is selected by CSB, W/RB,
and ENB with MBB HIGH. If the selected Port B bus size is
also 36 bits, then the usable width of the Mail2 Register em-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43683AV | 3.3V 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 16K x36 單向同步先進(jìn)先出帶總線匹配) |
| CY7C43664AV | 3.3V 4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 4K x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
| CY7C43644AV | 3.3V 1Kx36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 1K x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
| CY7C43684AV | 3.3V 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 16K x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
| CY7C43666AV | 3.3V 4K x36/x18x2 Tri Bus FIFO(3.3V 4K x36/x18x2 三路總線先進(jìn)先出) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43664-7AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43682-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683-10AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V SYNC FIFO W/BUS MATCHING 16K X36 (NOT IDT COMPAT) - Bulk |
| CY7C43684-10AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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