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參數(shù)資料
| 型號(hào)： | CY7C43663AV |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 4K x36 單向同步先進(jìn)先出帶總線匹配) |
| 中文描述： | 3.3 4K的x36單向同步FIFO瓦特/總線匹配（3.3 4K的x36單向同步先進(jìn)先出帶總線匹配） |
| 文件頁數(shù)： | 19/28頁 |
| 文件大小： | 420K |
| 代理商： | CY7C43663AV |
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CY7C43643AV
CY7C43663AV/CY7C43683AV
19
PRELIMINARY
Notes:
34. If Port B is configured for word size, data can be written to the Mail2 register using B
(B
are don
’
t care inputs). In this first case A
17
will have valid
data (A
will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B
0
–
8
(B
9
–
35
are
“
don
’
t care
”
inputs).
In this second case, A
will have valid data (A
9
–
35
will be indeterminate).
35. Clocks are free-running in this case.
36. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t
RTR
.
37. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t
RTR
to update these flags.
Switching Waveforms
(continued)
t
ENH
t
ENS
t
ENH
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
DH
t
DS
W1
t
PMF
t
PMF
t
EN
t
MDV
t
PMR
t
ENS
t
ENH
t
DIS
FIFO2 Output Register
W1 (Remains valid in Mail2 Register after read)
CLKB
CSB
W/RB
MBB
ENB
B
0
–
35
CLKA
MBF2
CSA
W/RA
MBA
ENA
A
0
35
Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes)
[34]
FIFO Retransmit Timing
ENB
RT1
t
PRT
t
RTR
EFB/FFA
[34, 35, 36, 37]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43683AV | 3.3V 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 16K x36 單向同步先進(jìn)先出帶總線匹配) |
| CY7C43664AV | 3.3V 4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 4K x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
| CY7C43644AV | 3.3V 1Kx36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 1K x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
| CY7C43684AV | 3.3V 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 16K x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
| CY7C43666AV | 3.3V 4K x36/x18x2 Tri Bus FIFO(3.3V 4K x36/x18x2 三路總線先進(jìn)先出) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43664-7AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43682-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683-10AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V SYNC FIFO W/BUS MATCHING 16K X36 (NOT IDT COMPAT) - Bulk |
| CY7C43684-10AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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