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參數(shù)資料
| 型號： | CY7C43646 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 1K x36/x18x2 Tri Bus FIFO(1K x36/x18x2 三路總線 先進(jìn)先出) |
| 中文描述： | 一千x36/x18x2三總線的FIFO（每1000 x36/x18x2三路總線先進(jìn)先出） |
| 文件頁數(shù)： | 30/40頁 |
| 文件大?。?/td> | 577K |
| 代理商： | CY7C43646 |
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CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
30
PRELIMINARY
Signal Description
Master Reset (MRS1, MRS2)
Each of the two FIFO memories of the CY7C436X6 undergoes
a complete reset by taking its associated Master Reset
(MRS1, MRS2) input LOW for at least four Port A clock (CLKA)
and four Port B clock (CLKB) LOW-to-HIGH transitions. The
Master Reset inputs can switch asynchronously to the clocks.
A Master Reset initializes the internal read and write pointers
and forces the Full/Input Ready flag (FFA/IRA, FFC/IRC) LOW,
the Empty/Output Ready flag (EFA/ORA, EFB/ORB) LOW, the
Almost Empty flag (AEA, AEB) LOW, and the Almost Full flag
(AFA, AFC) HIGH. A Master Reset also forces the Mailbox flag
(MBF1, MBF2) of the parallel mailbox register HIGH. After a
Master Reset, the FIFO
’
s Full/Input Ready flag is set HIGH
after two clock cycles to begin normal operation. A Master Re-
set must be performed on the FIFO after power-up, before data
is written to its memory.
A LOW-to-HIGH transition on a FIFO Master Reset (MRS1,
MRS2) input latches the value of the Big Endian (BE) input or
determines the order by which bytes are transferred through
Port B.
A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2)
input latches the values of the Flag select (FS0, FS1) and Se-
rial Programming Mode (SPM) inputs for choosing the Almost
Full and Almost Empty offset programming method (see Al-
most Empty and Almost Full flag offset programming below).
Partial Reset (PRS1, PRS2)
Each of the two FIFO memories of the CY7C436X6 undergoes
a limited reset by taking its associated Partial Reset (PRS1,
PRS2) input LOW for at least four Port A clock (CLKA) and four
Port B clock (CLKB) LOW-to-HIGH transitions. The Partial Re-
set inputs can switch asynchronously to the clocks. A Partial
Reset initializes the internal read and write pointers and forces
the Full/Input Ready flag (FFA/IRA, FFC/IRC) LOW, the Emp-
ty/Output Ready flag (EFA/ORA, EFB/ORB) LOW, the Almost
Empty flag (AEA, AEB) LOW, and the Almost Full flag (AFA,
AFC) HIGH. A Partial Reset also forces the Mailbox flag
(MBF1, MBF2) of the parallel mailbox register HIGH. After a
Partial Reset, the FIFO
’
s Full/Input Ready flag is set HIGH
after two clock cycles to begin normal operation.
Whatever flag offsets, programming method (parallel or seri-
al), and timing mode (FWFT or CY Standard mode) are cur-
rently selected at the time a Partial Reset is initiated, those
settings will remain unchanged upon completion of the reset
operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Master Reset would be in-
convenient.
Big Endian/First-Word Fall-Through (BE/FWFT)
This is a dual-purpose pin. At the time of Master Reset, the BE
select function is active, permitting a choice of Big or Little
Endian byte arrangement for data written to or read from Port
B. This selection determines the order by which bytes (or
words) of data are transferred through this port. For the follow-
ing illustrations, assume that a byte (or word) bus size has
been selected for Port B. (Note that when Port B is configured
for a long-word size, the Big Endian function has no application
and the BE input is a
“
don
’
t care.
”
)
A HIGH on the BE/FWFT input when the Master Reset (MRS1
and MRS2) inputs go from LOW to HIGH will select a Big En-
dian arrangement. When data is moving in the direction from
Port A to Port B, the most significant byte (word) of the long-
word written to Port A will be read from Port B first; the least
significant byte (word) of the long-word written to Port A will be
read from Port B last. When data is moving in the direction
from Port C to Port A, the byte (word) written to Port C first will
be read from Port A as the most significant byte (word) of the
long-word; the byte (word) written to Port C last will be read
from Port A as the least significant byte (word) of the long-
word.
A LOW on the BE/FWFT input when the Master Reset (MRS1
and MRS2) inputs go from LOW to HIGH will select a Little
Endian arrangement. When data is moving in the direction
from Port A to Port B, the least significant byte (word) of the
long-word written to Port A will be read from Port B first; the
most significant byte (word) of the long-word written to Port A
will be read from Port B last. When data is moving in the direc-
tion from Port C to Port A, the byte (word) written to Port C first
will be read from port A as the least significant byte (word) of
the long-word; the byte (word) written to Port C last will be read
from Port A as the most significant byte (word) of the long-
word.
After Master Reset, the FWFT select function is active, permit-
ting a choice between two possible timing modes: CY Stan-
dard Mode or First-Word Fall-Through (FWFT) Mode. Once
the Master Reset (MRS1, MRS2) input is HIGH, a HIGH on the
BE/FWFT input during the next LOW-to-HIGH transition of
CLKA (for FIFO1) and CLKB (for FIFO2) will select CY Stan-
dard Mode. This mode uses the Empty Flag function (EFA,
EFB) to indicate whether or not there are any words present in
the FIFO memory. It uses the Full Flag function (FFA, FFC) to
indicate whether or not the FIFO memory has any free space
for writing. In CY Standard Mode, every word read from the
FIFO, including the first, must be requested using a formal
read operation.
Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW
on the BE/FWFT input at the second LOW-to-HIGH transition
of CLKA (for FIFO1) and CLKC (for FIFO2) will select FWFT
Mode. This mode uses the Output Ready function (ORA,
ORB) to indicate whether or not there is valid data at the data
outputs (A
0
–
35
or B
0
–
17
). It also uses the Input Ready function
(IRA, IRC) to indicate whether or not the FIFO memory has
any free space for writing. In the FWFT mode, the first word
written to an empty FIFO goes directly to data outputs, no read
request necessary. Subsequent words must be accessed by
performing a formal read operation.
Following Master Reset, the level applied to the BE/FWFT in-
put to choose the desired timing mode must remain static
throughout the FIFO operation.
Programming the Almost Empty and Almost Full Flags
Four registers in the CY7C436X6 are used to hold the offset
values for the Almost Empty and Almost Full flags. The Port B
Almost Empty flag (AEB) offset register is labeled X1 and the
Port A Almost Empty flag (AEA) offset register is labeled X2.
The Port A Almost Full flag (AFA) offset register is labeled Y1
and the Port C Almost Full flag (AFC) offset register is labeled
Y2. The index of each register name corresponds with preset
values during the reset of a FIFO, programmed in parallel us-
ing the FIFO
’
s Port A data inputs, or programmed in serial
using the Serial Data (SD) input (see
Table 1
).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43666 | 4K x36/x18x2 Tri Bus FIFO(4K x36/x18x2 三路總線先進(jìn)先出) |
| CY7C43686 | 16K x36/x18x2 Tri Bus FIFO(16K x36/x18x2 三路總線先進(jìn)先出) |
| CY7C43662AV | 3.3V 4K x36 x2 Bidirectional Synchronous FIFO(3.3V 4K x36 x2 雙向同步先進(jìn)先出) |
| CY7C43682AV | 3.3V 16K x36 x2 Bidirectional Synchronous FIFO(3.3V 16K x36 x2 雙向同步先進(jìn)先出) |
| CY7C43663AV | 3.3V 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 4K x36 單向同步先進(jìn)先出帶總線匹配) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43663-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43664-7AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43682-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683-10AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V SYNC FIFO W/BUS MATCHING 16K X36 (NOT IDT COMPAT) - Bulk |
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