參數(shù)資料
型號: CY7C43646
廠商: Cypress Semiconductor Corp.
英文描述: 1K x36/x18x2 Tri Bus FIFO(1K x36/x18x2 三路總線 先進(jìn)先出)
中文描述: 一千x36/x18x2三總線的FIFO(每1000 x36/x18x2三路總線先進(jìn)先出)
文件頁數(shù): 22/40頁
文件大?。?/td> 577K
代理商: CY7C43646
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
22
PRELIMINARY
Notes:
33. If Port B size is word or byte, t
is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.
34. t
is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than t
SKEW1
, then IRA may transition HIGH one CLKA cycle later than shown.
Switching Waveforms
(continued)
t
CLKH
t
CLKL
t
ENS
t
ENH
t
A
LOW
HIGH
FIFO1 Full
LOW
HIGH
t
ENS
t
ENH
t
WFF
t
WFF
t
CLKH
t
CLKL
t
CLK
t
CLK
t
SKEW1[34]
t
DH
t
DS
t
ENH
t
ENS
Previous Word in
FIFO1 Output Register
Next Word From FIFO1
To FIFO1
CLKB
CSB
MBB
RENB
EFB/ORB
B
0
17
CLKA
FFA/IRA
CSA
W/RA
MBA
ENA
A
0
35
IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)
[33]
相關(guān)PDF資料
PDF描述
CY7C43666 4K x36/x18x2 Tri Bus FIFO(4K x36/x18x2 三路總線先進(jìn)先出)
CY7C43686 16K x36/x18x2 Tri Bus FIFO(16K x36/x18x2 三路總線先進(jìn)先出)
CY7C43662AV 3.3V 4K x36 x2 Bidirectional Synchronous FIFO(3.3V 4K x36 x2 雙向同步先進(jìn)先出)
CY7C43682AV 3.3V 16K x36 x2 Bidirectional Synchronous FIFO(3.3V 16K x36 x2 雙向同步先進(jìn)先出)
CY7C43663AV 3.3V 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 4K x36 單向同步先進(jìn)先出帶總線匹配)
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