參數(shù)資料
型號: CY7C43632
廠商: Cypress Semiconductor Corp.
英文描述: 512 x36 x2 Bidirectional Synchronous FIFO(512 x36 x2 雙向同步先進(jìn)先出)
中文描述: 512 x36 x2雙向同步FIFO(512 x36 x2雙向同步先進(jìn)先出)
文件頁數(shù): 16/31頁
文件大?。?/td> 463K
代理商: CY7C43632
CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
16
PRELIMINARY
Note:
22. t
is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than t
SKEW1
, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
Switching Waveforms
(continued)
EFA Flag Timing and First Data Read when FIFO2 is Empty (CY Standard Mode)
t
CLKH
t
CLKL
t
ENS
t
ENH
t
ENS
t
ENH
t
A
t
DS
W1
LOW
t
DH
LOW
HIGH
FIFO2 Empty
LOW
LOW
LOW
W1
t
ENS
t
ENH
t
REF
t
REF
t
CLKH
t
CLKL
t
CLK
t
CLK
t
SKEW1[22]
CLKB
CSB
W/RB
MBB
ENB
FFB/IRB
B
0
35
CLKA
EFA/ORA
CSA
W/RA
MBA
ENA
A
0
35
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PDF描述
CY7C43622 256 x36 x2 Bidirectional Synchronous FIFO(256 x36 x2 雙向同步先進(jìn)先出)
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