參數(shù)資料
型號(hào)： CY7C4255-10
廠商： Cypress Semiconductor Corp.
英文描述： 8K/16K x 18 Deep Sync FIFOs
中文描述： 8K/16K × 18深同步FIFO的
文件頁(yè)數(shù)： 3/22頁(yè)
文件大?。?/td> 348K
代理商： CY7C4255-10
CY7C4255
CY7C4265
Document #: 38-06004 Rev. *B
Page 3 of 22
Signal Name
D
0 –17
Q
0–17
WEN
REN
WCLK
Description
Data Inputs
Data Outputs
Write Enable
Read Enable
Write Clock
I/O
I
O
I
I
I
Function
Data inputs for an 18-bit bus.
Data outputs for an 18-bit bus.
Enables the WCLK inpu.t
Enables the RCLK input.
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not
Full. When LD is asserted, WCLK writes data into the programmable flag-offset
register.
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-off-
set register.
Dual-Mode Pin:
Single device or width expansion – Half Full status flag.
Cascaded – Write Expansion Out signal, connected to WXI of next device.
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost-empty offset
value programmed into the FIFO. PAE is asynchronous when V
CC
/SMODE is tied
to V
CC
; it is synchronized to RCLK when V
CC
/SMODE is tied to V
SS
.
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when V
CC
/SMODE is tied to
V
CC
; it is synchronized to WCLK when V
CC
/SMODE is tied to V
SS
.
When LD is LOW, D
0–17
(Q
0–17
) are written (read) into (from) the programma-
ble-flag-offset register.
Dual-Mode Pin:
Cascaded – The first device in the daisy chain will have FL tied to V
SS
; all other
devices will have FL tied to V
CC
. In standard mode or width expansion, FL is tied
to V
SS
on all devices.
Not Cascaded – Tied to V
SS
. Retransmit function is also available in stand-alone
mode by strobing RT.
Cascaded – Connected to WXO of previous device.
Not Cascaded – Tied to V
SS
.
Cascaded – Connected to RXO of previous device.
Not Cascaded – Tied to V
SS
.
Cascaded – Connected to RXI of next device.
RCLK
Read Clock
I
WXO/HF
Write Expansion
Out/Half Full Flag
O
EF
FF
PAE
Empty Flag
Full Flag
Programmable
Almost Empty
O
O
O
PAF
Programmable
Almost Full
O
LD
Load
I
FL/RT
First Load/
Retransmit
I
WXI
Write Expansion
Input
Read Expansion
Input
Read Expansion
Output
Reset
I
RXI
I
RXO
O
RS
I
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are con-
nected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Dual-Mode Pin:
Asynchronous Almost Empty/Almost Full flags – tied to V
CC
.
Synchronous Almost Empty/Almost Full flags – tied to V
SS
.
(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)
OE
Output Enable
I
V
CC
/SMODE
Synchronous
Almost Empty/
Almost Full Flags
I
相關(guān)PDF資料
PDF描述
CY7C4255-15 8K/16K x 18 Deep Sync FIFOs
CY7C4255-25 8K/16K x 18 Deep Sync FIFOs
CY7C4255-35 8K/16K x 18 Deep Sync FIFOs
CY7C4265-10 8K/16K x 18 Deep Sync FIFOs
CY7C4265-15 8K/16K x 18 Deep Sync FIFOs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C4255-10AC 功能描述:IC DEEP SYNC FIFO 8KX18 64LQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
CY7C4255-10AXC 功能描述:IC DEEP SYNC FIFO 8KX18 64LQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
CY7C4255-10AXCT 功能描述:IC SYNC FIFO MEM 8KX18 64LQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
CY7C4255-15AXC 功能描述:IC SYNC FIFO MEM 8KX18 64LQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
CY7C4255V-10ASXC 功能描述:先進(jìn)先出 8K X18 LOW VOLTAGE DEEP SYNC 先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
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