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參數(shù)資料
| 型號： | CY7C4255-10 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 8K/16K x 18 Deep Sync FIFOs |
| 中文描述： | 8K/16K × 18深同步FIFO的 |
| 文件頁數(shù)： | 15/22頁 |
| 文件大小： | 348K |
| 代理商： | CY7C4255-10 |
CY7C4255
CY7C4265
Document #: 38-06004 Rev. *B
Page 15 of 22
Architecture
The CY7C4256/65 consists of an array of 8K/16K words of 18
bits each (implemented by a dual-port array of SRAM cells), a
read pointer, a write pointer, control signals (RCLK, WCLK,
REN, WEN, RS), and flags (EF, PAE, HF, PAF, FF). The
CY7C4255/65 also includes the control signals WXI, RXI, WXO,
RXO for depth expansion.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs go LOW after the falling edge of RS
only if OE is asserted. In order for the FIFO to reset to its default state,
a falling edge must occur on RS and the user must not read or write
while RS is LOW.
FIFO Operation
When the WEN signal is active (LOW), data present on the D
0 – 17
pins is written into the FIFO on each rising edge of the WCLK signal.
Similarly, when the REN signal is active LOW, data in the FIFO mem-
ory will be presented on the Q
0–17
outputs. New data will be present-
ed on each rising edge of RCLK while REN is active LOW and OE is
LOW. REN must set up t
ENS
before RCLK for it to be a valid read
function. WEN must occur tENS before WCLK for it to be a valid write
function.
An output enable (OE) pin is provided to three-state the Q
0–17
outputs when OE is deasserted. When OE is enabled (LOW), data in
the output register will be available to the Q
0–17
outputs after t
OE
. If
devices are cascaded, the OE function will only output data on the
FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and under flow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q
0–17
outputs
even after additional reads occur.
Programming
The CY7C4255/65 devices contain two 14-bit offset registers.
Data present on D
0 – 13
during a program write will determine the
distance from Empty (Full) that the Almost Empty (Almost Full) flags
become active. If the user elects not to program the FIFO’s flags, the
default offset values are used (see
Table 2
). When the Load LD pin
is set LOW and WEN is set LOW, data on the inputs D
0–13
is written
into the Empty offset register on the first LOW-to-HIGH transition of
the Write Clock (WCLK). When the LD pin and WEN are held LOW
then data is written into the Full offset register on the second
LOW-to-HIGH transition of the Write Clock (WCLK). The third transi-
tion of the Write Clock (WCLK) again writes to the Empty offset reg-
ister (see
Table 1
). Writing all offset registers does not have to occur
at one time. One or two offset registers can be written and then, by
bringing the LD pin HIGH, the FIFO is returned to normal read/write
operation. When the LD pin is set LOW, and WEN is LOW, the next
offset register in sequence is written.
The contents of the offset registers can be read on the output
lines when the LD pin is set LOW and REN is set LOW; then, data
can be read on the LOW-to-HIGH transition of the Read Clock
(RCLK).
Flag Operation
The CY7C4255/65 devices provide five flag pins to indicate
the condition of the FIFO contents. Empty and Full are syn-
chronous. PAE and PAF are synchronous if V
CC
/SMODE is tied to
V
SS
.
Full Flag
The Full Flag (FF) will go LOW when device is Full. Write operations
are inhibited whenever FF is LOW regardless of the state of WEN.
FF is synchronized to WCLK, i.e., it is exclusively updated by each
rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty. Read
operations are inhibited whenever EF is LOW, regardless of the state
of REN. EF is synchronized to RCLK, i.e., it is exclusively updated by
each rising edge of RCLK.
Programmable Almost Empty/Almost Full Flag
The CY7C4255/65 features programmable Almost Empty and
Almost Full Flags. Each flag can be programmed (described
in the Programming section) a specific distance from the cor-
responding boundary flags (Empty or Full). When the FIFO
contains the number of words or fewer for which the flags have
been programmed, the PAF or PAE will be asserted, signifying that
the FIFO is either Almost Full or Almost Empty. See
Table 2
for a
description of programmable flags.
When the SMODE pin is tied LOW, the PAF flag signal transition is
caused by the rising edge of the write clock and the PAE flag transition
is caused by the rising edge of the read clock.
Notes:
37. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Table 1. Write Offset Register
WCLK
[37]
0
0
LD
WEN
Selection
Writing to offset registers:
Empty Offset
Full Offset
0
1
No Operation
1
0
Write Into FIFO
1
1
No Operation
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C4255-15 | 8K/16K x 18 Deep Sync FIFOs |
| CY7C4255-25 | 8K/16K x 18 Deep Sync FIFOs |
| CY7C4255-35 | 8K/16K x 18 Deep Sync FIFOs |
| CY7C4265-10 | 8K/16K x 18 Deep Sync FIFOs |
| CY7C4265-15 | 8K/16K x 18 Deep Sync FIFOs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C4255-10AC | 功能描述:IC DEEP SYNC FIFO 8KX18 64LQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| CY7C4255-10AXC | 功能描述:IC DEEP SYNC FIFO 8KX18 64LQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| CY7C4255-10AXCT | 功能描述:IC SYNC FIFO MEM 8KX18 64LQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| CY7C4255-15AXC | 功能描述:IC SYNC FIFO MEM 8KX18 64LQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| CY7C4255V-10ASXC | 功能描述:先進先出 8K X18 LOW VOLTAGE DEEP SYNC 先進先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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