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參數(shù)資料
| 型號： | CY7C4231V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Low Voltage 2K x 9 Synchronous FIFOs(2Kx9低壓同步先進(jìn)先出（FIFO）) |
| 中文描述： | 低壓2K × 9同步FIFO的（2Kx9低壓同步先進(jìn)先出（FIFO）的） |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 291K |
| 代理商： | CY7C4231V |
CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Low Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
October 14, 1999
4241V
Features
High-speed, low-power, first-in, first-out (FIFO)
memories
64 x 9 (CY7C4421V)
256 x 9 (CY7C4201V)
512 x 9 (CY7C4211V)
1K x 9 (CY7C4221V)
2K x 9 (CY7C4231V)
4K x 9 (CY7C4241V)
8K x 9 (CY7C4251V)
High-speed 66-MHz operation (15-ns read/write cycle
time)
Low power (I
CC
= 20 mA)
3.3V operation for low power consumption and easy
integration into low-voltage systems
5V tolerant inputs V
IH max
= 5V
Fully asynchronous and simultaneous read and write
operation
Empty, Full, and Programmable Almost Empty and
Almost Full status flags
TTL compatible
Output Enable (OE) pin
Independent read and write enable pins
Center power and ground pins for reduced noise
Width expansion capability
Space saving 32-pin 7 mm x 7 mm TQFP
32-pin PLCC
Functional Description
The CY7C42X1V are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
are 9 bits wide. Programmable features include Almost Full/Al-
most Empty flags. These FIFOs provide solutions for a wide
variety of data buffering needs, including high-speed data ac-
quisition, multiprocessor interfaces, and communications buff-
ering.
These FIFOs have 9-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a Free-Running Clock (WCLK) and two Write
Enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled
in a similar manner by a Free-Running Read Clock (RCLK)
and two Read Enable Pins (REN1, REN2). In addition, the
CY7C42X1V has an Output Enable Pin (OE). The Read
(RCLK) and Write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock fre-
quencies up to 66 MHz are achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic
to direct the flow of data
.
Logic Block Diagram
Pin Configuration
42X1V–1
42X1V–2
THREE-STATE
OUTPUTREGISTER
READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER
READ
POINTER
RESET
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D0
8
RCLK
EF
PAE
PAF
FF
Q0
8
WEN1
WCLK
RS
OE
D64 x 9
8Kx 9
WEN2/LD
REN1 REN2
PLCC
Top View
42X1V–3
D
1
D
0
RCLK
REN2
V
CC
Q
8
Q
7
Q
6
Q
5
D
8
D
7
D
6
D
5
D
4
D
3
GND
REN1
WCLK
WEN2/LD
D
2
D
8
D
7
D
6
D
5
D
4
D
3
D
2
PAF
PAE
5
6
7
8
9
10
11
12
13
1
2
3
4
5
6
7
8
OE
4 3 2 1
3130
32
D
1
D
0
RCLK
REN2
GND
REN1
PAF
PAE
21
22
23
24
27
26
28
29
25
14151617181920
17
18
19
20
21
22
23
24
14 15 16
9 10 11 1213
31 30
32
2928 27
25
26
WEN1
RS
F
Q
0
Q
1
Q
2
Q
3
Q
4
E
F
Q
0
Q
1
Q
2
Q
3
Q
4
E
O
V
CC
Q
8
Q
7
Q
6
Q
5
WCLK
WEN2/LD
WEN1
R
TQFP
Top View
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C4421V | Low Voltage 64 x 9 Synchronous FIFOs(64x9低壓同步先進(jìn)先出（FIFO）) |
| CY7C4241V | Low Voltage 4K x 9 Synchronous FIFOs(4Kx9低壓同步先進(jìn)先出（FIFO）) |
| CY7C4251V | Low Voltage 8K x 9 Synchronous FIFOs(8Kx9低壓同步先進(jìn)先出（FIFO）) |
| CY7C4235V | 2K x 19 Synchronous FIFOs(2K x 18 同步先進(jìn)先出) |
| CY7C4205V | 256 x 18 Synchronous FIFOs(256 x 18 同步先進(jìn)先出) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C4231V-15JC | 功能描述:IC SYNC FIFO MEM 2KX9 LV 32-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| CY7C4231V-15JCT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C4231V-15JXC | 功能描述:IC SYNC FIFO MEM 2KX9 LV 32-PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| CY7C4231V-15JXCT | 功能描述:IC SYNC FIFO MEM 2KX9 32-PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| CY7C4231V-25AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 2K x 9 32-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:2KX9 LOW VOLTAGE SYNC FIFO - Bulk |
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