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參數(shù)資料
| 型號： | CY7C4235V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2K x 19 Synchronous FIFOs(2K x 18 同步先進先出) |
| 中文描述： | 2K × 19（2K × 18同步先進先出同步FIFO的） |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 564K |
| 代理商： | CY7C4235V |
64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4225V/4205V/4215V
CY7C4425V/4235V/4245V
Cypress Semiconductor Corporation
Document #: 38-06029 Rev. *C
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised September 7, 2005
Features
3.3V operation for low power consumption and easy
integration into low-voltage systems
High-speed, low-power, first-in first-out (FIFO)
memories
64 x 18 (CY7C4425V)
256 x 18 (CY7C4205V)
512 x 18 (CY7C4215V)
1K x 18 (CY7C4225V)
2K x 18 (CY7C4235V)
4K x 18 (CY7C4245V)
0.65
μ
CMOS
High-speed 67-MHz operation (15-ns read/write cycle
times)
Low power
— I
CC
= 30 mA
5V tolerant inputs (V
IH MAX
= 5V)
Fully asynchronous and simultaneous read and write
operation
Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
TTL-compatible
Retransmit function
Output Enable (OE) pin
Independent read and write enable pins
Supports free-running 50% duty cycle clock inputs
Width-Expansion Capability
Depth-Expansion Capability
64-pin 14 × 14 TQFP and 64-pin 10 × 10 STQFP
Pb-Free packages available
Functional Description
The CY7C42X5V are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
are 18 bits wide. The CY7C42X5V can be cascaded to
increase FIFO depth. Programmable features include Almost
Full/Almost Empty flags. These FIFOs provide solutions for a
wide variety of data buffering needs, including high-speed data
acquisition, multiprocessor interfaces, and communications
buffering.
These FIFOs have 18-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a Free-Running Clock (WCLK) and a Write
Enable pin (WEN).
When WEN is asserted, data is written into the FIFO on the
rising edge of the WCLK signal. While WEN is held active, data
is continually written into the FIFO on each cycle. The output
port is controlled in a similar manner by a Free-Running Read
Clock (RCLK) and a Read Enable pin (REN). In addition, the
CY7C42X5V have an Output Enable pin (OE). The read and
write clocks may be tied together for single-clock operation or
the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 66 MHz are
achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the Cascade Input (WXI,
RXI), Cascade Output (WXO, RXO), and First Load (FL) pins.
The WXO and RXO pins are connected to the WXI and RXI
pins of the next device, and the WXO and RXO pins of the last
device should be connected to the WXI and RXI pins of the
first device. The FL pin of the first device is tied to V
SS
and the
FL pin of all the remaining devices should be tied to V
CC
.
The CY7C42X5V provides five status pins. These pins are
decoded to determine one of five states: Empty, Almost Empty,
Half Full, Almost Full, and Full (see
Table 2
). The Half Full flag
shares the WXO pin. This flag is valid in the stand-alone and
width-expansion configurations. In the depth expansion, this
pin provides the expansion out (WXO) information that is used
to signal the next FIFO when it will be activated.
The Empty and Full flags are synchronous, i.e., they change
state relative to either the Read Clock (RCLK) or the write
clock (WCLK). When entering or exiting the Empty states, the
flag is updated exclusively by the RCLK. The flag denoting Full
states is updated exclusively by WCLK. The synchronous flag
architecture guarantees that the flags will remain valid from
one clock cycle to the next. As mentioned previously, the
Almost Empty/Almost Full flags become synchronous if the
V
CC
/SMODE is tied to V
SS
. All configurations are fabricated
using an advanced 0.65
P-Well CMOS technology. Input
ESD protection is greater than 2001V, and latch-up is
prevented by the use of guard rings.
CY7C4425V
/4205V/4215V
CY7C4225V
/4235V/4245V64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C4205V | 256 x 18 Synchronous FIFOs(256 x 18 同步先進先出) |
| CY7C4215V | 512 x 18 Synchronous FIFOs(512 x 18 同步先進先出) |
| CY7C4225V | 1K x 19 Synchronous FIFOs(1K x 18 同步先進先出) |
| CY7C4425V | 64 x 18 Synchronous FIFOs(64 x 18 同步先進先出) |
| CY7C4245V | 4K x 18 Synchronous FIFOs(4K x 18 同步先進先出) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C4235V-15ASC | 功能描述:IC SYNC FIFO MEM 2KX18 64LQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| CY7C4235V-15ASXC | 功能描述:先進先出 2K X18 LO VLTG SYNC 先進先出 COM RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| CY7C4241 WAF | 制造商:Cypress Semiconductor 功能描述: |
| CY7C4241-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 4K x 9 32-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:4K X 9 32 PIN IDT COMPAT SYNCH FIFO - Bulk |
| CY7C4241-10ACT | 制造商:Cypress Semiconductor 功能描述: |
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